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1. 发明授权

US11347922B2 Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement 有权
公开(公告)号：US11347922B2
公开(公告)日：2022-05-31
申请号：US17195094
申请日：2021-03-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hiranmay Biswas , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang
IPC分类号： G06F30/392 , G06F30/3947 , G06F30/3953 , G06F30/394 , H01L23/522 , H01L23/532 , H01L23/528 , H01L23/00
摘要： A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of the third segments.

2. 发明授权

US11211327B2 Via sizing for IR drop reduction 有权
公开(公告)号：US11211327B2
公开(公告)日：2021-12-28
申请号：US16731719
申请日：2019-12-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hiranmay Biswas , Chin-Shen Lin , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F30/394 , H01L23/528 , H01L27/02 , H01L27/118 , H01L21/768 , H01L23/522
摘要： A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

3. 发明授权

US09953122B2 Integrated circuit design method and associated non-transitory computer-readable medium 有权
公开(公告)号：US09953122B2
公开(公告)日：2018-04-24
申请号：US15210052
申请日：2016-07-14
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Yu-Jen Chang , Kuo-Nan Yang , Jui-Jung Hsu , Chih-Hung Wu , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/82 , G06F2217/84
摘要： An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.

4. 发明申请

US20160197068A1 Power Gating for Three Dimensional Integrated Circuits (3DIC) 审中-公开
公开(公告)号：US20160197068A1
公开(公告)日：2016-07-07
申请号：US15070904
申请日：2016-03-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Ju Chao , Chou-Kun Lin , Yi-Chuin Tsai , Yen-Hung Lin , Po-Hsiang Huang , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： H01L27/02 , H01L23/50 , H01L27/06 , H01L27/092 , H01L21/822 , H01L21/8238
CPC分类号： H01L27/0207 , H01L21/324 , H01L21/768 , H01L21/8221 , H01L21/823475 , H01L21/823871 , H01L23/50 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L27/0203 , H01L27/0688 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

5. 发明申请

US20160118462A1 FinFET with an Asymmetric Source/Drain Structure and Method of Making Same 审中-公开
标题翻译：具有不对称源极/漏极结构的FinFET及其制造方法
公开(公告)号：US20160118462A1
公开(公告)日：2016-04-28
申请号：US14987351
申请日：2016-01-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Kuo-Nan Yang , Ming-Hsiang Song , Ta-Pen Guo
IPC分类号： H01L29/08 , H01L21/306 , H01L29/78 , H01L21/283 , H01L29/417 , H01L27/088 , H01L29/66 , H01L21/8234
CPC分类号： H01L29/0847 , H01L21/283 , H01L21/30604 , H01L21/823418 , H01L21/823431 , H01L21/823814 , H01L21/845 , H01L27/0886 , H01L27/0924 , H01L29/41758 , H01L29/66477 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/6681 , H01L29/7835 , H01L29/785
摘要： Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.
摘要翻译：本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。

6. 发明授权

US09262573B2 Cell having shifted boundary and boundary-shift scheme 有权
标题翻译：移位边界和边界移位方案
公开(公告)号：US09262573B2
公开(公告)日：2016-02-16
申请号：US13791406
申请日：2013-03-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
摘要翻译：实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。

7. 发明授权

US09047433B2 Cell and macro placement on fin grid 有权
标题翻译：细胞和宏放置在鳍状网格上
公开(公告)号：US09047433B2
公开(公告)日：2015-06-02
申请号：US13874027
申请日：2013-04-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.
摘要翻译：芯片包括至少一个标准单元，其包括与第一边界相对的第一边界和第二边界。第一边界和第二边界平行于第一方向。所述至少一个标准单元还包括第一多个FinFET，其包括平行于所述第一方向的第一半导体鳍片。芯片还包括至少一个存储器宏，其具有与第三边界相反的第三边界和第四边界。第三边界和第四边界与第一方向平行。至少一个存储器宏包括第二多个FinFET，其包括平行于第一方向的第二半导体鳍片。所述至少一个标准单元和所述至少一个存储器宏中的所有半导体鳍具有等于所述第一和第二半导体鳍的最小间距的整数倍的间距。

8. 发明申请

US20140258952A1 Cell Having Shifted Boundary and Boundary-Shift Scheme 有权
标题翻译：移位边界和边界移位方案
公开(公告)号：US20140258952A1
公开(公告)日：2014-09-11
申请号：US13791406
申请日：2013-03-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5081
摘要： An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
摘要翻译：实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。在一个实施例中，小区移位方案包括移动位置和路由边界以防止布局与示意图（LVS）网表和后仿真网表之间的不匹配。

9. 发明申请

US20140245248A1 Cell and Macro Placement on Fin Grid 有权
标题翻译：电网和宏放置在电网上
公开(公告)号：US20140245248A1
公开(公告)日：2014-08-28
申请号：US13874027
申请日：2013-04-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Nan Yang , Chou-Kun Lin , Jerry Chang-Jui Kao , Yi-Chuin Tsai , Chien-Ju Chao , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.
摘要翻译：芯片包括至少一个标准单元，其包括与第一边界相对的第一边界和第二边界。第一边界和第二边界平行于第一方向。所述至少一个标准单元还包括第一多个FinFET，其包括平行于所述第一方向的第一半导体鳍片。芯片还包括至少一个存储器宏，其具有与第三边界相反的第三边界和第四边界。第三边界和第四边界与第一方向平行。至少一个存储器宏包括第二多个FinFET，其包括平行于第一方向的第二半导体鳍片。所述至少一个标准单元和所述至少一个存储器宏中的所有半导体鳍片具有等于所述第一和第二半导体鳍片的最小间距的整数倍的间距。

10. 发明授权

US11600568B2 Layouts for conductive layers in integrated circuits 有权
公开(公告)号：US11600568B2
公开(公告)日：2023-03-07
申请号：US17351711
申请日：2021-06-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wan-Yu Lo , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang , Meng-Xiang Lee , Hao-Tien Kan , Jhih-Hong Ye
IPC分类号： H01L23/528 , H01L23/522
摘要： Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

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