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1. 发明授权

US11600568B2 Layouts for conductive layers in integrated circuits 有权
公开(公告)号：US11600568B2
公开(公告)日：2023-03-07
申请号：US17351711
申请日：2021-06-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wan-Yu Lo , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang , Meng-Xiang Lee , Hao-Tien Kan , Jhih-Hong Ye
IPC分类号： H01L23/528 , H01L23/522
摘要： Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

2. 发明授权

US11251124B2 Power grid structures and method of forming the same 有权
公开(公告)号：US11251124B2
公开(公告)日：2022-02-15
申请号：US15729281
申请日：2017-10-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hiranmay Biswas , Chi-Yeh Yu , Chung-Hsing Wang , Kuo-Nan Yang , Stefan Rusu , Chin-Shen Lin
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522 , G06F30/394
摘要： An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

3. 发明授权

US10936785B2 Inter-cell leakage-reducing method of generating layout diagram and system for same 有权
公开(公告)号：US10936785B2
公开(公告)日：2021-03-02
申请号：US16547065
申请日：2019-08-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Jia Han Lin
IPC分类号： G06F30/398 , G06F119/18 , G03F7/20 , H01L27/092 , H01L27/02 , G06F30/392
摘要： A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.

4. 发明授权

US10509888B1 System and method for forming integrated device 有权
公开(公告)号：US10509888B1
公开(公告)日：2019-12-17
申请号：US16134419
申请日：2018-09-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Hiranmay Biswas , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F17/50
摘要： A method for forming an integrated device is provided. The method includes the following operations. A first circuit layout having a first power path and a second power path is provided. The first power path and the second power path are aligned in a first direction. A first pitch between the first power path and the second power path is analyzed. It is determined whether the first pitch is less than a threshold pitch. If the first pitch is less than the threshold pitch, the second power path is modified in a second direction. The second direction is perpendicular to the first direction.

5. 发明授权

US10467364B2 Characterizing cell using input waveforms with different tail characteristics 有权
公开(公告)号：US10467364B2
公开(公告)日：2019-11-05
申请号：US15400519
申请日：2017-01-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： King-Ho Tam , Yen-Pin Chen , Wen-Hao Chen , Chung-Hsing Wang
IPC分类号： G06F17/50
摘要： In some embodiments, a plurality of first input waveforms having a same first input transition characteristic and different first tail characteristics are obtained. A first cell is characterized using the plurality of first input waveforms to create a plurality of corresponding first entries associated with the first input transition characteristic in a library. A design layout is generated based on performing circuit simulation using at least one entry of the plurality of first entries. An integrated circuit (IC) chip is manufactured using the design layout.

6. 发明授权

US10055531B2 Layout checking method for advanced double patterning photolithography with multiple spacing criteria 有权
公开(公告)号：US10055531B2
公开(公告)日：2018-08-21
申请号：US14622009
申请日：2015-02-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Chung-Hsing Wang , King-Ho Tam , Yuan-Te Hou , Chin-Chang Hsu , Meng-Kai Hsu
IPC分类号： G06F17/50 , H01L27/02 , H01L27/11582
CPC分类号： G06F17/5081 , H01L27/0207 , H01L27/11582 , H01L28/00
摘要： In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.

7. 发明授权

US09589885B2 Device having multiple-layer pins in memory MUX1 layout 有权
标题翻译：在存储器MUX1布局中具有多层引脚的器件
公开(公告)号：US09589885B2
公开(公告)日：2017-03-07
申请号：US14835788
申请日：2015-08-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hung-Jen Liao , Jung-Hsuan Chen , Chien Chi Tien , Ching-Wei Wu , Jui-Che Tsai , Hong-Chen Cheng , Chung-Hsing Wang
IPC分类号： H01L23/00 , H01L23/50 , H01L27/11 , H01L23/532 , H01L27/02 , H01L23/528 , H01L23/498 , H01L23/522
CPC分类号： H01L23/50 , H01L23/49811 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L23/53204 , H01L27/0203 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.
摘要翻译：集成电路（IC）存储器件包括第一导电层。 IC存储器件还包括在第一导电层上的第二导电层。 IC存储器件还包括与第一导电层电耦合的第一型引脚盒。 IC存储器件还包括与第一类型引脚盒不同的第二型引脚盒，与第二导电层电耦合。

8. 发明授权

US09501602B2 Electromigration-aware layout generation 有权
标题翻译：电迁移感知布局生成
公开(公告)号：US09501602B2
公开(公告)日：2016-11-22
申请号：US14255325
申请日：2014-04-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Nitesh Katta , Jerry Chang-Jui Kao , Chin-Shen Lin , Yi-Chuin Tsai , Chou-Kun Lin , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5036 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.
摘要翻译：在一些实施例中，在一种方法中，执行设计布局的放置。设计布局包括电力轨道段，几个上级电力线和几个电池。上层电力线在电力轨道段上交叉并限制在上层电力线与电力轨道段相交的位置。电池通过电源轨段供电。对于每个电池，获得在电池的相应SW期间通过电力轨道段的相应电流。确定具有重叠SW的一组或多组细胞。获得使用每组单元的各自电流的一组或多组单元的电力轨道段的一个或多个EM用途。当电力轨道段的一个或多个EM使用中的任何一个导致电力轨道段的EM敏感性时，调整设计布局。

9. 发明授权

US09471738B2 Method and apparatus for capacitance extraction 有权
标题翻译：电容提取方法和装置
公开(公告)号：US09471738B2
公开(公告)日：2016-10-18
申请号：US14615084
申请日：2015-02-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Cheng Chou , Tsung-Han Wu , Ke-ying Su , Hsien-Hsin Sean Lee , Chung-Hsing Wang
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
摘要翻译：一种方法包括处理集成电路的布局以确定集成电路的一个或多个组件的一个或多个属性。该方法还包括从与制造集成电路相关联的处理文件中提取一个或多个处理参数。基于包括在处理文件中的一个或多个逻辑功能的计算，从处理文件中提取一个或多个处理参数。计算基于一个或多个属性。该方法还包括基于一个或多个处理参数和包括在处理文件中的电容确定规则来计算集成电路的至少两个分量之间的电容值。一个或多个处理参数，一个或多个逻辑功能或电容确定规则中的至少一个可以基于用户输入进行编辑。

10. 发明授权

US09367660B2 Electromigration-aware layout generation 有权
标题翻译：电迁移感知布局生成
公开(公告)号：US09367660B2
公开(公告)日：2016-06-14
申请号：US14218147
申请日：2014-03-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Nitesh Katta , Jerry Chang-Jui Kao , Chin-Shen Lin , Yi-Chuin Tsai , Chien-Ju Chao , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5068 , G06F17/5072 , G06F17/5077
摘要： In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.
摘要翻译：在一些实施例中，在一种方法中，接收多个单元的单元布局。对于每个单元，基于单元格布局中的单元的输出引脚的几何形状来确定影响要在设计布局中耦合到单元的输出引脚的互连的几何形状的相应约束。

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