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1. 发明授权

US10054969B2 Monolithic reference architecture with burst mode support 有权
公开(公告)号：US10054969B2
公开(公告)日：2018-08-21
申请号：US15259368
申请日：2016-09-08
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Anand Subramanian , Anand Kannan , Sunil Rafeeque , Venakatesh Guduri
IPC分类号： G05F1/10 , G05F3/02 , G05F1/565 , G05F1/625 , G05F3/16 , G05F1/575
CPC分类号： G05F1/575
摘要： A reference circuit may include a bandgap reference stage, a filter stage, and a buffer stage. The reference stage may be configured to generate a reference voltage or current. The filter stage may be coupled to the reference stage and may be configured to receive the reference voltage or current, filter noise from the reference voltage or current, receive a buffer output voltage or current, and filter noise from the buffer output voltage or current. The buffer stage may be coupled to the filter stage and may be configured to isolate the reference stage and the filter stage from a loading effect of a load circuit and generate a reference signal based on the reference voltage or current to drive the load circuit.

2. 发明申请

US20150188561A1 NOVEL TECHNIQUE TO COMBINE A COARSE ADC AND A SAR ADC 有权
标题翻译：合并ADC和ADC的新技术
公开(公告)号：US20150188561A1
公开(公告)日：2015-07-02
申请号：US14255269
申请日：2014-04-17
申请人： Texas Instruments Incorporated
发明人： Subramanian Jagdish Narayan , Anand Kannan
IPC分类号： H03M1/38 , H03M1/66 , H03M1/06
CPC分类号： H03M1/144 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： A successive approximation register analog to digital converter (SAR ADC) is disclosed. The SAR ADC receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.
摘要翻译：公开了逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB（最低有效位）电容器阵列。零交叉检测器耦合到电荷共享DAC。过零检测器产生数字输出。粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。将预定义的偏移量添加到粗略ADC的残差。逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。

3. 发明授权

US11409317B2 Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators 有权
公开(公告)号：US11409317B2
公开(公告)日：2022-08-09
申请号：US15962515
申请日：2018-04-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Praful Kumar Parakh , Anand Kannan , Sunil Rafeeque
IPC分类号： G05F3/24
摘要： A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

4. 发明授权

US09971375B2 Piecewise correction of errors over temperature without using on-chip temperature sensor/comparators 有权
公开(公告)号：US09971375B2
公开(公告)日：2018-05-15
申请号：US14949390
申请日：2015-11-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Praful Kumar Parakh , Anand Kannan , Sunil Rafeeque
IPC分类号： G05F3/24
CPC分类号： G05F3/245
摘要： A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

5. 发明申请

US20220350360A1 Piecewise Correction of Errors Over Temperature without Using On-Chip Temperature Sensor/Comparators 有权
公开(公告)号：US20220350360A1
公开(公告)日：2022-11-03
申请号：US17868684
申请日：2022-07-19
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Praful Kumar Parakh , Anand Kannan , Sunil Rafeeque
IPC分类号： G05F3/24
摘要： A temperature dependent correction circuit includes a first supply source, a second supply source, a rectifying circuit, and a reference. The first supply source is configured to supply a first signal that varies with temperature along a first constant or continuously variable slope. The second supply source is configured to supply a second signal that varies with temperature along a second constant or continuously variable slope. The rectifying circuit is configured to receive the first and second signal, rectify the first signal to produce a first rectified signal, and add the first rectified signal to the second signal to produce a correction signal. The reference is configured to receive the correction signal.

6. 发明授权

US09148166B2 Adding predefined offset to coarse ADC residue output to SAR 有权
标题翻译：将预定义的偏移量添加到粗略的ADC残差输出到SAR
公开(公告)号：US09148166B2
公开(公告)日：2015-09-29
申请号：US14255269
申请日：2014-04-17
申请人： Texas Instruments Incorporated
发明人： Subramanian Jagdish Narayan , Anand Kannan
IPC分类号： H03M1/06 , H03M1/38 , H03M1/66
CPC分类号： H03M1/144 , H03M1/0604 , H03M1/0695 , H03M1/468
摘要： A successive approximation register analog to digital converter (SAR ADC) receives an input voltage and a plurality of reference voltages. The SAR ADC includes a charge sharing DAC. The charge sharing DAC includes an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit) capacitors. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A coarse ADC (analog to digital converter) receives the input voltage and generates a coarse output. A predefined offset is added to a residue of the coarse ADC. A successive approximation register (SAR) state machine is coupled to the coarse ADC and the zero crossing detector and, generates a plurality of control signals. The plurality of control signals operates the charge sharing DAC in a sampling mode, an error-correction mode and a conversion mode.
摘要翻译：逐次逼近寄存器模数转换器（SAR ADC）接收输入电压和多个参考电压。 SAR ADC包含一个电荷共享DAC。电荷共享DAC包括一个MSB（最高有效位）电容器阵列和一个LSB（最低有效位）电容器阵列。零交叉检测器耦合到电荷共享DAC。过零检测器产生数字输出。粗略的ADC（模数转换器）接收输入电压并产生粗略的输出。将预定义的偏移量添加到粗略ADC的残差。逐次逼近寄存器（SAR）状态机耦合到粗略ADC和过零检测器，并产生多个控制信号。多个控制信号以采样模式，纠错模式和转换模式操作电荷共享DAC。

7. 发明授权

US09118342B2 Low power excess loop delay compensation technique for delta-sigma modulators 有权
标题翻译：用于Δ-Σ调制器的低功率多余环路延迟补偿技术
公开(公告)号：US09118342B2
公开(公告)日：2015-08-25
申请号：US14033047
申请日：2013-09-20
申请人： Texas Instruments Incorporated
发明人： Vikas Singh , Anand Kannan , Ashish Lachhwani
IPC分类号： H03M3/00 , H03M1/00 , H03M1/46
CPC分类号： H03M3/372 , H03M1/002 , H03M1/46 , H03M3/37 , H03M3/422 , H03M3/454
摘要： A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.
摘要翻译：具有输入级和输出级的Δ-Σ调制器。输入级接收模拟输入信号和第一数模转换器（DAC）的输出。输入级产生处理后的误差信号。附加求和装置接收处理的误差信号。输出级接收附加求和装置的输出并产生延迟的数字输出信号。差分器和第一个数模转换器（DAC）接收延迟的数字输出信号作为反馈信号。第二DAC接收微分器的输出，并向另外的负反馈系数乘法器提供输出。附加求和装置接收附加负反馈系数乘法器的输出。

8. 发明授权

US11509217B2 Stable digital integrator circuit for boost converter 有权
公开(公告)号：US11509217B2
公开(公告)日：2022-11-22
申请号：US16950346
申请日：2020-11-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Anandha Ruban Tiruchengode Tirumurugga Bupathi , Anand Kannan , Dileep Kumar Ramesh Bhat
IPC分类号： H02M3/157 , H04R3/02 , H03M1/78
摘要： An electrical device includes an integrated circuit having device circuitry and a boost converter coupled to the device circuitry. The boost converter includes a digital integrator circuit having: a first comparator; a second comparator; a counter configured to count up, count down, and pause based on a first output signal provided by the first comparator and based on a second output signal provided by the second comparator; and a digital-to-analog converter (DAC) configured to provide a feedback adjustment signal for the boost converter based on a count value provided by the counter.

9. 发明授权

US11152904B2 Programmable gain amplifier with programmable resistance 有权
公开(公告)号：US11152904B2
公开(公告)日：2021-10-19
申请号：US16789540
申请日：2020-02-13
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Anand Subramanian , Tanmay Halder , Anand Kannan
IPC分类号： H03F3/45 , H03G3/30 , H03M1/12
摘要： A circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front end (AFE) having an AFE input and an AFE output. The AFE output is coupled the ADC's input. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (OP AMP) with first and second OPAMP inputs. The AFE also including a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balance resistances. The first balance resistance is coupled to the first and second OP AMP inputs, and the second balance resistance is coupled to the first and second OP AMP inputs.

10. 发明授权

US10763889B1 Analog-to-digital converter with dynamic range enhancer 有权
公开(公告)号：US10763889B1
公开(公告)日：2020-09-01
申请号：US16661456
申请日：2019-10-23
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Uttam Kumar Agarwal , Anand Kannan , Ramamurthy Vishweshwara , Anand Subramanian , Pedro Ramon Gelabert , Diljith Mathal Thodi , Abhijit Anant Patki
IPC分类号： H03M3/00 , H03G3/00 , H03G1/00 , H03G3/30 , H03M7/34 , H03M1/12 , H03M1/06 , H03G5/02
摘要： A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

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