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1. 发明授权

US11429028B2 Method of cutting conductive patterns 有权
公开(公告)号：US11429028B2
公开(公告)日：2022-08-30
申请号：US16683150
申请日：2019-11-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Tsong-Hua Ou , Wen-Hao Chen
IPC分类号： H05K3/06 , G03F7/20 , H05K3/00 , G06F30/39 , G03F1/70 , H01L21/3213
摘要： A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

2. 发明授权

US09563731B2 Cell boundaries for self aligned multiple patterning abutments 有权
标题翻译：自对准多图案化基台的单元边界
公开(公告)号：US09563731B2
公开(公告)日：2017-02-07
申请号：US14210490
申请日：2014-03-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Li-Chun Tien , Pin-Dai Sue , Ching Hsiang Chang , Wen-Hao Chen , Cheng-I Huang
IPC分类号： G06F17/50 , G03F7/20 , G03F1/70
CPC分类号： G06F17/5068 , G03F1/70 , G03F7/70433 , G03F7/70466
摘要： A system and method of determining a cell layout are disclosed. The method includes receiving a circuit design corresponding to a predetermined circuit design, the circuit design having a first set of cells and abutting adjacent cells in the first set of cells, the abutted cells having a first boundary pattern therebetween. The first boundary pattern is exchanged with a second boundary pattern based on a number or positions of signal wires in the first boundary pattern. A cell layout for use in a patterning process can then be determined, the cell layout including the second boundary pattern.
摘要翻译：公开了一种确定单元布局的系统和方法。所述方法包括接收与预定电路设计相对应的电路设计，所述电路设计具有第一组单元并邻接所述第一组单元中的相邻单元，所述邻接单元在其间具有第一边界图案。基于第一边界图案中的信号线的数量或位置，第一边界图案与第二边界图案交换。然后可以确定用于图案化处理的单元格布局，单元布局包括第二边界图案。

3. 发明授权

US09262570B2 Layout boundary method 有权
标题翻译：布局边界法
公开(公告)号：US09262570B2
公开(公告)日：2016-02-16
申请号：US13919037
申请日：2013-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Wen-Hao Chen , Ho Che Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.
摘要翻译：本公开的一些实施例涉及实现与多图案化过程兼容的布局的方法和装置。两个或多个单元电池被构造成具有满足多图案化工艺的性质的布局，并且分解成两种或更多种颜色以支持多图案化工艺。活动布局特征与两个单位单元之间的共享边界处的虚拟线合并。在共享边界处的两个活动布局特征之间短路的情况下，自动布局后方法可以重新排列共享边界附近的布局特征，以分离活动布局特征以实现单元功能，同时满足多图案化属性。

4. 发明授权

US09223924B2 Method and system for multi-patterning layout decomposition 有权
标题翻译：多图案布局分解的方法和系统
公开(公告)号：US09223924B2
公开(公告)日：2015-12-29
申请号：US14043890
申请日：2013-10-02
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Chin-Chang Hsu , Yuan-Te Hou , Godina Ho , Wen-Hao Chen , Wen-Ju Yang
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G06F17/5081 , G03F1/00 , G03F1/36 , G03F1/70 , G03F7/70283 , G03F7/70466 , G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.
摘要翻译：集成电路的单层布局的一部分是多图案化的。用于布局分解的方法包括确定相邻图案对之间的间隔，以及生成具有多个子图的冲突图，其中相应的顶点对应于每个相应的子图。每个相应子图中的图案被划分为至少第一组和第二组，其中的每一组被分配为通过第一掩模或第二掩模中的分别不同的一个在单层上被图案化。该方法还包括在处理器中基于预定的一组标准来确定每个相应子图中的多个模式中的颜色规则违规的计数; 并且在每个子图中，将子图中的第一组图案分配给第一掩码或第二掩码中的一个，导致颜色规则违规的较小数量。

5. 发明申请

US20140282344A1 LAYOUT BOUNDARY METHOD 有权
标题翻译：布局边界方法
公开(公告)号：US20140282344A1
公开(公告)日：2014-09-18
申请号：US13919037
申请日：2013-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Wen-Hao Chen , Ho Che Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.
摘要翻译：本公开的一些实施例涉及实现与多图案化过程兼容的布局的方法和装置。两个或多个单元电池被构造成具有满足多图案化工艺的性质的布局，并且分解成两种或更多种颜色以支持多图案化工艺。活动布局特征与两个单位单元之间的共享边界处的虚拟线合并。在共享边界处的两个活动布局特征之间短路的情况下，自动布局后方法可以重新排列共享边界附近的布局特征，以分离活动布局特征以实现单元功能，同时满足多图案化属性。

6. 发明申请

US20200081348A1 METHOD OF CUTTING CONDUCTIVE PATTERNS 审中-公开
公开(公告)号：US20200081348A1
公开(公告)日：2020-03-12
申请号：US16683150
申请日：2019-11-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Tsong-Hua Ou , Wen-Hao Chen
IPC分类号： G03F7/20 , H01L21/3213 , G06F17/50 , G03F1/70 , H05K3/06 , H05K3/00
摘要： A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

7. 发明授权

US09087170B2 Cell layout design and method 有权
标题翻译：细胞布局设计和方法
公开(公告)号：US09087170B2
公开(公告)日：2015-07-21
申请号：US14011790
申请日：2013-08-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Yuan-Te Hou , Li-Chun Tien , Hui-Zhong Zhuang , Fang-Yu Fan , Wen-Hao Chen , Ting Yu Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068
摘要： A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.
摘要翻译：一种方法包括将一个或多个单元与选择指南进行比较，并将满足选择准则的单元存储在非瞬态计算机可读存储介质中，以基于该比较创建单元库。选择指南确定单元格内边界引脚的合适位置。

8. 发明授权

US08875067B2 Reusable cut mask for multiple layers 有权
标题翻译：可重复使用的切割面具多层
公开(公告)号：US08875067B2
公开(公告)日：2014-10-28
申请号：US13893424
申请日：2013-05-14
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Yuan-Te Hou , Wen-Hao Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/70
摘要： The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.
摘要翻译：本公开涉及一种形成可用于多个设计级别的可重复使用的切割掩模或修剪掩模的方法，以及相关联的装置。在一些实施例中，通过确定用于可重复使用的切割掩模或可重复使用的修剪掩模的多个掩模切口的位置来执行该方法。然后，形状沿着具有多个设计级别的路由路径路由。路由路径在形成不同形状的位置处与多个掩模切割中的一个或多个相交，所述不同形状连接共享相同电网的集成芯片的节点。通过在多个设计级别上布置形状以与多个掩模切口中的一个或多个相交，切割掩模可以在多个等级之间重复使用，因此在制造期间降低掩模成本。

9. 发明授权

US10509322B2 Method of cutting conductive patterns 有权
公开(公告)号：US10509322B2
公开(公告)日：2019-12-17
申请号：US15189311
申请日：2016-06-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Tsong-Hua Ou , Wen-Hao Chen
IPC分类号： H05K3/06 , G03F7/20 , H05K3/00 , G03F1/70 , G06F17/50 , H01L21/3213
摘要： A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

10. 发明授权

US09380709B2 Method of cutting conductive patterns 有权
标题翻译：切割导电图案的方法
公开(公告)号：US09380709B2
公开(公告)日：2016-06-28
申请号：US13924681
申请日：2013-06-24
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chin-Hsiung Hsu , Huang-Yu Chen , Tsong-Hua Ou , Wen-Hao Chen
IPC分类号： H05K3/10 , H05K3/06 , H05K3/00
CPC分类号： G03F7/2022 , G03F1/70 , G06F17/5068 , H01L21/3213 , H05K3/0005 , H05K3/0082 , H05K3/06 , H05K3/068 , H05K2201/09781 , H05K2203/0557 , H05K2203/1476 , Y10T29/49156
摘要： A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.
摘要翻译：一种方法包括用第一金属图案在衬底上图案化层; 在相对于所述基板的第一位置使用切割掩模，以执行用于从所述第一图案内的第一区域去除材料的第一切割图案; 并且使用相同的切割掩模在相对于衬底上的相同层的第二位置执行第二切割图案，用于从衬底上的相同层的第二金属图案中的第二区域去除材料。

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