专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20160188654A1 RULE BASED DATA NORMALIZATION UTILIZING MULTI-KEY SORTING 审中-公开
标题翻译：基于规则的数据正规化利用多重分类
公开(公告)号：US20160188654A1
公开(公告)日：2016-06-30
申请号：US14582510
申请日：2014-12-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Pao-Po Hou , Derek C. Tao , Liang-Yu Chen , Shaojie Xu , Kuoyuan Hsu
IPC分类号： G06F17/30
CPC分类号： G06F17/30958
摘要： Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.
摘要翻译：公开了用于有效检索相邻测量值以便能够快速执行基于规则的纠错的方法和系统。一方面，公开了一种使用多键分类的数据归一化方法。在一些实施例中，该方法包括由数据组织引擎接收包括对应的相邻数据的一组未校正的数据。在各种实施例中，数据组织引擎通过构造有向非循环图（DAG）来组织未校正的数据，其中DAG包括多个节点。在一些实施例中，数据组织引擎可以遍历多个节点以检索对应的相邻数据。在检索相邻数据时，基于规则的校正引擎可以利用检索到的对应的相邻数据来校正未校正的数据。

2. 发明授权

US08935641B2 Semiconductor circuit design method, memory compiler and computer program product 有权
标题翻译：半导体电路设计方法，内存编译器和计算机程序产品
公开(公告)号：US08935641B2
公开(公告)日：2015-01-13
申请号：US13800751
申请日：2013-03-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5036 , G06F2217/82
摘要： A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted.
摘要翻译：半导体电路包括重复块的阵列，每个块具有装置，以及至少一个连接块的装置的信号线。生成半导体电路的模型以包括对应于该阵列的至少一个第一块的功能区域和对应于阵列的至少一个第二块的加载区域。在功能区域中，提取至少一个信号线的寄生参数和至少一个第一块的装置。在装载区域中，提取至少一个信号线的寄生参数，但是不提取至少一个第二块的装置的寄生参数。

3. 发明授权

US10031982B2 Rule based data normalization utilizing multi-key sorting 有权
公开(公告)号：US10031982B2
公开(公告)日：2018-07-24
申请号：US14582510
申请日：2014-12-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Pao-Po Hou , Derek C. Tao , Liang-Yu Chen , Shaojie Xu , Kuoyuan Hsu
IPC分类号： G06F17/50 , G06F17/30
摘要： Methods and systems for efficient retrieval of neighboring measurement values in order to enable fast execution of rule-based error correction are disclosed. In one aspect, a method for data normalization using multi-key sorting is disclosed. In some embodiments, the method includes receiving, by a data organization engine, a set of uncorrected data including corresponding neighboring data. In various embodiments, the data organization engine organizes the uncorrected data by construction of a directed acyclic graph (DAG), where the DAG includes a plurality of nodes. In some embodiments, the data organization engine may traverse the plurality of nodes to retrieve the corresponding neighboring data. Upon retrieval of the neighboring data, a rule-based correction engine may correct the uncorrected data utilizing the retrieved corresponding neighboring data.

4. 发明授权

US09298875B2 Semiconductor circuit design method, memory compiler and computer program product 有权
标题翻译：半导体电路设计方法，内存编译器和计算机程序产品
公开(公告)号：US09298875B2
公开(公告)日：2016-03-29
申请号：US14567383
申请日：2014-12-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5036 , G06F2217/82
摘要： A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.
摘要翻译：设计半导体电路的方法包括生成半导体电路的模型。该模型包括对应于半导体电路的第一块的功能区域和对应于半导体电路的第二块的加载区域，其中第一块通过信号线连接到第二块。该方法还包括在功能区域中提取信号线的寄生参数和第一块的装置。该方法还包括在加载区域中提取信号线的寄生参数，而不提取第二块的装置的寄生参数。

5. 发明授权

US08997031B2 Timing delay characterization method, memory compiler and computer program product 有权
标题翻译：时序延迟表征方法，内存编译器和计算机程序产品
公开(公告)号：US08997031B2
公开(公告)日：2015-03-31
申请号：US13800005
申请日：2013-03-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031 , G06F2217/84
摘要： In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.
摘要翻译：在定时延迟表征方法中，将半导体电路的输入端子和输出端子之间的信号路径分为输入级，处理级和输出级。在输入端的输入参数的各种输入参数值下模拟输入级的操作，以获得与输入级相关联的相应的外在输入定时延迟。模拟处理级的操作以获得与处理级相关联的固有定时延迟。在输出端的输出参数的各种输出参数值下模拟输出级的操作，以获得与输出级相关联的相应的外在输出定时延迟。基于外部输入定时延迟，非本征输出定时延迟和固有定时延迟来生成或填充定时延迟数据存储器。

6. 发明授权

US10176282B2 Timing delay characterization method, memory compiler and computer program product 有权
公开(公告)号：US10176282B2
公开(公告)日：2019-01-08
申请号：US14638444
申请日：2015-03-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shaojie Xu , Yukit Tang , Pao-Po Hou , Derek C. Tao , Annie-Li-Keow Lum
IPC分类号： G06F17/50
摘要： A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式