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1. 发明授权

US06507532B1 Semiconductor memory device having row-related circuit operating at high speed 失效
标题翻译：具有行相关电路的半导体存储器件以高速工作
公开(公告)号：US06507532B1
公开(公告)日：2003-01-14
申请号：US09722687
申请日：2000-11-28
申请人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
发明人： Takeshi Fujino , Kazunari Inoue , Akira Yamazaki , Kazutami Arimoto
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C8/18 , G11C11/4087
摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.
摘要翻译：中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号时钟周期，用于传输到每个存储器子块。备用确定电路与时钟信号异步地执行备用确定。可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

2. 发明授权

US06418067B1 Semiconductor memory device suitable for merging with logic 失效
标题翻译：半导体存储器件适用于与逻辑电路合并
公开(公告)号：US06418067B1
公开(公告)日：2002-07-09
申请号：US09592454
申请日：2000-06-09
申请人： Naoya Watanabe , Akira Yamazaki , Kazutami Arimoto , Takeshi Fujino , Isamu Hayashi , Hideyuki Noda
发明人： Naoya Watanabe , Akira Yamazaki , Kazutami Arimoto , Takeshi Fujino , Isamu Hayashi , Hideyuki Noda
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C11/4076 , G11C29/846
摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.
摘要翻译：读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。通过替换数据线对执行备用位修复。列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。

3. 发明授权

US06404695B1 Semiconductor memory device including a plurality of memory blocks arranged in rows and columns 失效
标题翻译：半导体存储器件包括以行和列排列的多个存储块
公开(公告)号：US06404695B1
公开(公告)日：2002-06-11
申请号：US09877026
申请日：2001-06-11
申请人： Takeshi Fujino , Akira Yamazaki
发明人： Takeshi Fujino , Akira Yamazaki
IPC分类号： G11C800
CPC分类号： G11C11/4087
摘要： A DRAM includes two main column selecting lines provided at each sense amplifier zone, eight sub column selecting lines provided at each sense amplifier zone to correspond to each memory block, two sub decoder column selecting lines provided at each sub decoder zone, a sub column decoder provided at each crossing portion of the sense amplifier zone and the sub decoder zone to select one sub column selecting line from corresponding eight sub column selecting lines in accordance with a signal from the two main column selecting lines and the two sub decoder column selecting lines. The area of the sense amplifier zone can be reduced compared to that of a conventional DRAM in which all signal lines for column selection were provided at a sense amplifier zone.
摘要翻译： DRAM包括在每个读出放大器区域提供的两个主列选择线，在每个读出放大器区域处提供的八个子列选择线，以对应于每个存储块，在每个子解码器区提供的两个子解码器列选择线，子列解码器设置在感测放大器区域和子解码器区域的每个交叉部分处，以根据来自两个主列选择线和两个子解码器列选择线的信号从相应的八个子列选择线中选择一个子列选择线。与传统DRAM相比，读出放大器区域的面积可以减少，其中用于列选择的所有信号线都设置在读出放大器区域。

4. 发明授权

US07047461B2 Semiconductor integrated circuit device with test data output nodes for parallel test results output 失效
标题翻译：半导体集成电路器件具有测试数据输出节点，用于并行测试结果输出
公开(公告)号：US07047461B2
公开(公告)日：2006-05-16
申请号：US10322676
申请日：2002-12-19
申请人： Akira Yamazaki , Takeshi Fujino , Atsuo Mangyo
发明人： Akira Yamazaki , Takeshi Fujino , Atsuo Mangyo
IPC分类号： G11C29/00
CPC分类号： G11C29/1201 , G11C29/24
摘要： A semiconductor integrated circuit device includes test data output nodes arranged in a width of a plurality of bits and an internal data bus, greater in bit width than the test data output nodes, for transferring internal data. A predetermined number of bits of the internal data on the internal data bus are compared with bits of test expected value data equal in bit width to the test data output nodes for each bit. The predetermined number of bits of the internal data are selected in accordance with a test address signal. The bits selected is compared with the respective bits of the test expected valued data. Data indicating respective comparison results are output to the test data output nodes in parallel.
摘要翻译：半导体集成电路器件包括以多个位宽度布置的测试数据输出节点和内部数据总线，其位宽比测试数据输出节点更大，用于传送内部数据。将内部数据总线上的内部数据的预定数量的比特与针对每个比特的测试数据输出节点的比特宽度相等的测试期望值数据的比特进行比较。根据测试地址信号选择内部数据的预定位数。所选择的比较与测试期望值数据的各个比特。指示各个比较结果的数据被并行地输出到测试数据输出节点。

5. 发明授权

US08258604B2 Semiconductor device and method of manufacturing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08258604B2
公开(公告)日：2012-09-04
申请号：US12647445
申请日：2009-12-26
申请人： Koji Bando , Kazuyuki Misumi , Tatsuhiko Akiyama , Naoki Izumi , Akira Yamazaki
发明人： Koji Bando , Kazuyuki Misumi , Tatsuhiko Akiyama , Naoki Izumi , Akira Yamazaki
IPC分类号： H01L23/552
CPC分类号： H01L23/49503 , G11C11/16 , H01L23/552 , H01L24/32 , H01L24/33 , H01L24/45 , H01L24/48 , H01L27/228 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/4824 , H01L2224/48247 , H01L2224/48257 , H01L2224/4826 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01042 , H01L2924/01046 , H01L2924/01061 , H01L2924/01064 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/1306 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00 , H01L2924/01026 , H01L2924/01028 , H01L2924/3512 , H01L2224/05599 , H01L2924/00012
摘要： To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device.A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.
摘要翻译：提供一种通过提高包括MRAM器件的半导体器件中的外部磁场的电阻来提高MRAM器件的数据保持特性的技术。第一磁屏蔽材料经由第一管芯附着膜设置在管芯焊盘上。然后，半导体芯片通过第二芯片附着膜安装在第一磁屏蔽材料上。此外，第二磁屏蔽材料通过第三芯片附着膜设置在半导体芯片的上方。也就是说，半导体芯片被布置成被第一磁屏蔽材料和第二磁屏蔽材料夹在中间。此时，当第二磁屏蔽材料的平面区域小于第一磁屏蔽材料的平面区域时，第二磁屏蔽材料的厚度比第一磁屏蔽材料的厚度厚。

6. 发明申请

US20070170573A1 SEMICONDUCTOR DEVICE, INTERPOSER CHIP AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件，半导体器件的插片芯片和制造方法
公开(公告)号：US20070170573A1
公开(公告)日：2007-07-26
申请号：US11617239
申请日：2006-12-28
申请人： Soshi KURODA , Naoya Yasuda , Hideyuki Arakawa , Akira Yamazaki , Koji Bando
发明人： Soshi KURODA , Naoya Yasuda , Hideyuki Arakawa , Akira Yamazaki , Koji Bando
IPC分类号： H01L23/02
CPC分类号： H01L23/5386 , H01L21/6836 , H01L23/3128 , H01L23/544 , H01L23/552 , H01L24/27 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2223/5442 , H01L2223/54426 , H01L2223/54473 , H01L2223/6611 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/13144 , H01L2224/274 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48225 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48478 , H01L2224/48479 , H01L2224/48599 , H01L2224/49171 , H01L2224/49173 , H01L2224/73265 , H01L2224/78301 , H01L2224/83191 , H01L2224/8385 , H01L2224/85001 , H01L2224/85051 , H01L2224/85205 , H01L2224/85399 , H01L2224/85986 , H01L2224/92 , H01L2224/92247 , H01L2225/0651 , H01L2225/06527 , H01L2225/06562 , H01L2225/06596 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/01037 , H01L2924/01047 , H01L2924/01058 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10161 , H01L2924/10253 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/20753 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/85186 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2924/20752 , H01L2224/4554
摘要： The semiconductor device with which bonding wires cannot contact easily is offered.In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected by a bonding wire. Therefore, since the transfer pressure of liquid resin for sealing can be weakened with a wire, contact of the wires by deformation of a wire can be prevented.
摘要翻译：提供接合线不容易接触的半导体器件。在该半导体装置中，将存储芯片层叠在布线基板的表面上，在存储芯片的表面配置有微型计算机芯片和插入式芯片，微型计算机芯片的焊盘和插入器芯片的焊盘几乎布置圆形通过接合线连接。因此，由于可以用线弱化用于密封的液态树脂的转印压力，因此可以防止由于电线的变形引起的电线的接触。

7. 发明授权

US07009781B2 Zoom lens mechanism partly foldable and retractable 失效
标题翻译：变焦镜头机构部分可折叠和缩回
公开(公告)号：US07009781B2
公开(公告)日：2006-03-07
申请号：US10873347
申请日：2004-06-22
申请人： Atsushi Oshima , Akira Yamazaki , Yasutaka Koga
发明人： Atsushi Oshima , Akira Yamazaki , Yasutaka Koga
IPC分类号： G02B15/14
CPC分类号： G02B7/102
摘要： A zoom lens mechanism foldable and retractable to be used in a digital still camera to control zooming of the zoom lens uses programmed data written in a micro controller unit (hereinafter referred to as MCU) instead of the conventional cylindrical grooved cams that are usually used to mechanically control zooming of a zoom lens of a digital still camera, and the assembly of the second lens group is rotatable inside the lens barrel, and the first lens group can be folded and retracted into the space provided by the rotation of the second lens assembly.
摘要翻译：可变形和可缩回以用于数字静态照相机以控制变焦镜头变焦的变焦透镜机构使用写在微控制器单元（以下称为MCU）中的编程数据代替常规的圆柱形凹槽凸轮，通常用于机械地控制数字静态照相机的变焦镜头的变焦，并且第二透镜组的组合可在透镜镜筒内旋转，并且第一透镜组可被折叠并缩回到由第二透镜组件的旋转所提供的空间。

8. 发明授权

US06995468B2 Semiconductor apparatus utilizing a preparatory stage for a chip assembly 有权
标题翻译：半导体装置利用芯片组装的准备阶段
公开(公告)号：US06995468B2
公开(公告)日：2006-02-07
申请号：US10798345
申请日：2004-03-12
申请人： Shunichi Abe , Tetsuya Uebayashi , Naoki Izumi , Akira Yamazaki
发明人： Shunichi Abe , Tetsuya Uebayashi , Naoki Izumi , Akira Yamazaki
IPC分类号： H01L23/34 , H01L21/48
CPC分类号： H01L24/83 , H01L21/2007 , H01L23/49513 , H01L24/27 , H01L24/29 , H01L24/32 , H01L25/0657 , H01L25/50 , H01L2224/274 , H01L2224/32145 , H01L2224/83191 , H01L2224/8385 , H01L2225/0651 , H01L2924/01004 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/07802
摘要： In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.
摘要翻译：在半导体器件制造方法中，将具有多个芯片的多个晶片承载并放置在管芯接合器中。从多个晶片取出的芯片分别结合在一起，并通过结合层叠在堆叠中以形成芯片组件。通过接合层将芯片组合到芯片焊盘。因此，芯片接合器能够将由多个芯片组成的芯片组件接合到芯片焊盘，使得用于将多个芯片接合到管芯焊盘的管芯接合工艺的处理时间相对较短，半导体制造设备以提高生产率生产半导体器件，规模相对较小，需要相对较低的设备投资。

9. 发明授权

US06737736B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06737736B2
公开(公告)日：2004-05-18
申请号：US09892539
申请日：2001-06-28
申请人： Shunichi Abe , Tetsuya Uebayashi , Naoki Izumi , Akira Yamazaki
发明人： Shunichi Abe , Tetsuya Uebayashi , Naoki Izumi , Akira Yamazaki
IPC分类号： H01L23495
CPC分类号： H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2224/05599 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/85399 , H01L2224/92247 , H01L2225/06562 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01057 , H01L2924/01068 , H01L2924/01082 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.
摘要翻译：通过在不增加面积的情况下减小半导体器件的厚度来实现小型化和致密化的半导体器件和制造方法。端子电极在平面图中布置在半导体芯片布置的区域的外部。下半导体芯片与端子电极高度重叠，上半导体芯片放置在下半导体芯片的上方，将上下半导体芯片连接到端子电极，封装树脂封装上下半导体芯片，电线封装树脂的底面与端子电极的底面共面。

10. 发明授权

US06700434B2 Substrate bias voltage generating circuit 失效
标题翻译：基板偏压生成电路
公开(公告)号：US06700434B2
公开(公告)日：2004-03-02
申请号：US09879914
申请日：2001-06-14
申请人： Nobuyuki Fujii , Fukashi Morishita , Mihoko Akiyama , Akira Yamazaki , Mako Kobayashi , Yasuhiko Taito
发明人： Nobuyuki Fujii , Fukashi Morishita , Mihoko Akiyama , Akira Yamazaki , Mako Kobayashi , Yasuhiko Taito
IPC分类号： G05F1575
CPC分类号： G05F3/205 , H03K3/0315 , H03K3/354
摘要： Oscillation outputs which are different for respective detector signals output from a first detector circuit and a second detector circuit, are obtained from a first ring oscillator and a second ring oscillator respectively corresponding to the detector circuits. A selector selects and outputs one of the oscillation outputs. Accordingly, it is sufficient to provide only one pump circuit in a circuit producing a substrate bias voltage.
摘要翻译：从分别对应于检测器电路的第一环形振荡器和第二环形振荡器获得对从第一检测器电路和第二检测器电路输出的相应检测器信号不同的振荡输出。选择器选择并输出其中一个振荡输出。因此，在产生衬底偏置电压的电路中仅提供一个泵电路就足够了。

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