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1. 发明授权

US06762477B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06762477B2
公开(公告)日：2004-07-13
申请号：US10191469
申请日：2002-07-10
申请人： Tatsuya Kunikiyo
发明人： Tatsuya Kunikiyo
IPC分类号： H01L2900
CPC分类号： H01L21/84 , H01L21/76264 , H01L21/76283 , H01L27/1203
摘要： Provided is a semiconductor device using an SOI substrate which can suppress a leakage current with the potential of a channel formation region fixed. Specifically, by an FTI (26) an SOI substrate (14) is divided into a PMOS formation region and an NMOS formation region. The FTI (26) extends from the upper surface of a silicon layer (17) to the upper surface of a BOX layer (16). A body contact region (9) is selectively formed in an upper surface of the silicon substrate (14). The body contact region (9) and a channel formation region (4p) are isolated from each other, by a PTI (31). An N+ type channel stopper layer (30) is formed in the portion of the silicon layer (14) which is sandwiched between the bottom surface of the PTI (31) and the upper surface of the BOX layer (16). The body contact region (9) and the channel formation region (4p) are electrically connected to each other, through the channel stopper layer (30).
摘要翻译：提供一种使用SOI衬底的半导体器件，其可以在固定沟道形成区域的电位的情况下抑制漏电流。具体地，通过FTI（26），将SOI衬底（14）分成PMOS形成区域和NMOS形成区域。 FTI（26）从硅层（17）的上表面延伸到BOX层（16）的上表面。在硅衬底（14）的上表面中选择性地形成体接触区域（9）。通过PTI（31）将体接触区域（9）和通道形成区域（4p）彼此隔离。在夹在PTI（31）的底表面和BOX层（16）的上表面之间的硅层（14）的部分中形成N +型通道阻挡层（30）。体接触区域（9）和通道形成区域（4p）通过沟道阻挡层（30）彼此电连接。

2. 发明授权

US06429105B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06429105B1
公开(公告)日：2002-08-06
申请号：US09612960
申请日：2000-07-10
申请人： Tatsuya Kunikiyo
发明人： Tatsuya Kunikiyo
IPC分类号： H01L213205
CPC分类号： H01L21/76814 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L21/76819 , H01L21/76825 , H01L21/7684 , H01L21/76843 , H01L23/53238 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device is provided. A TEOS film (1) is formed, and then an FSG film (2) is formed on the TEOS film (1) by a CVD or PVD process. The CVD or PVD of the FSG film (2) is continued so that noble gas atoms are introduced into the FSG film (2) to form a noble gas atom containing layer (3). Next, using a photoresist (4) formed on the noble gas atom containing layer (3) as a mask, the noble gas atom containing layer (3) and the FSG film (2) are etched in the order named. After the photoresist (4) is removed, a barrier metal (6) and a copper film (7) are formed on an entire surface of a resultant structure. The copper film (7) and the barrier metal (6) are polished away in the order named by a CMP process until an upper surface of the noble gas atom containing layer (3) is exposed. Parts of the copper film (7) which are left unpolished become copper interconnect lines (9) filling trenches (5). The method can reduce a wiring capacitance between the adjacent interconnect lines.
摘要翻译：提供一种制造半导体器件的方法。形成TEOS膜（1），然后通过CVD或PVD工艺在TEOS膜（1）上形成FSG膜（2）。 FSG膜（2）的CVD或PVD继续进行，使得惰性气体原子被引入到FSG膜（2）中以形成含惰性气体原子的层（3）。接着，使用形成在上述惰性气体原子含有层（3）上的光致抗蚀剂（4）作为掩模，按所述顺序对惰性气体原子含有层（3）和FSG膜（2）进行蚀刻。在除去光致抗蚀剂（4）之后，在所得结构的整个表面上形成阻挡金属（6）和铜膜（7）。将铜膜（7）和阻挡金属（6）以CMP工序命名的顺序被抛光，直到暴露含惰性气体原子的层（3）的上表面。未被抛光的铜膜（7）的部分成为填充沟槽（5）的铜互连线（9）。该方法可以减少相邻互连线之间的布线电容。

3. 发明授权

US5845105A Method of simulating semiconductor manufacture with process functions according to user application 失效
标题翻译：根据用户应用模拟具有过程功能的半导体制造方法
公开(公告)号：US5845105A
公开(公告)日：1998-12-01
申请号：US551307
申请日：1995-11-01
申请人： Tatsuya Kunikiyo , Katsumi Eikyu , Kenichiro Sonoda , Masato Fujinaga , Kiyoshi Ishikawa , Norihiko Kotani
发明人： Tatsuya Kunikiyo , Katsumi Eikyu , Kenichiro Sonoda , Masato Fujinaga , Kiyoshi Ishikawa , Norihiko Kotani
IPC分类号： H01L21/02 , G06F17/50 , H01L21/00 , H01L27/02 , G06F9/455
CPC分类号： G06F17/5045 , H01L27/0207
摘要： A method of manufacturing a semiconductor device wherein the device is manufactured according to extracted process parameters. The process parameters are extracted as a set of optimum process parameters which satisfy an intended specification using process functions. The process functions describe a characteristic of the semiconductor device, and are determined using experimental values and/or simulated values. The process parameters may then be transmitted online to a factory.
摘要翻译：一种制造半导体器件的方法，其中根据提取的工艺参数制造器件。过程参数被提取为使用过程功能满足期望规格的一组最佳过程参数。过程功能描述了半导体器件的特性，并且使用实验值和/或模拟值来确定。然后可以将工艺参数在线传输到工厂。

4. 发明授权

US07230435B2 Capacitance measurement circuit 失效
标题翻译：电容测量电路
公开(公告)号：US07230435B2
公开(公告)日：2007-06-12
申请号：US10760449
申请日：2004-01-21
申请人： Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto , Kyoji Yamashita
发明人： Tatsuya Kunikiyo , Tetsuya Watanabe , Toshiki Kanamoto , Kyoji Yamashita
IPC分类号： G01R27/26 , G01R27/02
CPC分类号： G01R27/2605
摘要： A CBCM circuit is capable of separately measuring each component of a measuring target capacitance. A node (N1) is electrically connected to a terminal (P2) between the drains of PMOS and NMOS transistors (MP2, MN2). As a target capacitance forming part, a coupling capacitance (Cc) is formed between the node (N1) and a node (N2). The node (N2) is connected to a pad (58) through the terminal (P2) and an NMOS transistor (MN3), and a node (N3) is connected to a terminal (P3) between the drains of PMOS and NMOS transistors (MP1, MN1). A reference capacitance (Cref) is formed at the node (N3) as a dummy capacitance. Currents (Ir, It) supplied from a power source to the nodes (N3, N1) are measured with current meters (61, 62), respectively and a current (Im) induced from the node (N2) and flowing to a ground level is measured with a current meter (63).
摘要翻译： CBCM电路能够单独测量测量目标电容的每个分量。节点（N 1）电连接到PMOS和NMOS晶体管（MP 2，MN 2）的漏极之间的端子（P 2）。作为目标电容形成部，在节点（N 1）和节点（N 2）之间形成耦合电容（C SUB）。节点（N 2）经由端子（P 2）和NMOS晶体管（MN 3）连接到焊盘（58），并且节点（N 3）连接到端子（N 3）之间的端子（P 3） PMOS和NMOS晶体管（MP 1，MN 1）。在节点（N 3）处形成参考电容（C SUB）作为虚拟电容。分别用电流计（61,62）从电源向节点（N 3，N 1）提供的电流（I，R，I，T）使用电流计（63）测量从节点（N 2）感应并流到地平面的电流（I SUB）。

5. 发明授权

US06950369B2 Magnetic memory device capable of passing bidirectional currents through the bit lines 失效
标题翻译：能够将双向电流通过位线的磁存储器件
公开(公告)号：US06950369B2
公开(公告)日：2005-09-27
申请号：US10797199
申请日：2004-03-11
申请人： Tatsuya Kunikiyo , Katsumi Eikyu
发明人： Tatsuya Kunikiyo , Katsumi Eikyu
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01F10/08 , H01F10/32 , H01L21/8246 , H01L27/105 , H01L43/08
CPC分类号： B82Y10/00 , G11C11/15 , G11C11/16 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2924/01019 , H01L2924/01021 , H01L2924/01025 , H01L2924/01039 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.
摘要翻译：多个字线（WL1）彼此并联设置，并且多个位线（BL 1）彼此平行地设置，与上述字线（WL 1）相交。 MRAM单元（MC2）形成在字线和它们之间的位线的交点处。提供MRAM单元（MC 3），使得箭头所示的容易轴相对于位线和字线具有45度的角度。因此，实现了能够切换写入功耗的MRAM，并且进一步实现了能够减少擦除和写入操作所需的时间的MRAM。

6. 发明授权

US06770550B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US06770550B2
公开(公告)日：2004-08-03
申请号：US09441889
申请日：1999-11-17
申请人： Tatsuya Kunikiyo
发明人： Tatsuya Kunikiyo
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/26506 , H01L21/28088 , H01L23/544 , H01L29/1033 , H01L29/4941 , H01L29/518 , H01L29/66545 , H01L29/66583 , H01L29/6659 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： After a channel layer (7) containing nitrogen is formed in a channel region (5) in the main surface of a semiconductor substrate (1), a gate insulating film (9) and insulating films (10) are formed as oxide film by a thermal oxidation on the main surface of the semiconductor substrate (1). The insulating films (10) are thicker than the gate insulating film (9) because the oxidation reaction is suppressed in the nitrogen-introduced region. Further, stresses caused by the oxidation are suppressed-around the connections between the gate insulating film (9) and the insulating films (10). Accordingly, reduction in leakage current and improvement of gate insulating film reliability are compatibly realized.
摘要翻译：在半导体衬底（1）的主表面中的通道区域（5）中形成含有氮的沟道层（7）之后，通过栅极绝缘膜（9）和绝缘膜（10）形成氧化膜在半导体衬底（1）的主表面上的热氧化。绝缘膜（10）比栅极绝缘膜（9）厚，因为在氮导入区域抑制了氧化反应。此外，围绕栅极绝缘膜（9）和绝缘膜（10）之间的连接，抑制由氧化引起的应力。因此，能够兼容地实现漏电流的降低和栅绝缘膜的可靠性的提高。

7. 发明授权

US06741495B2 Magnetic memory device and magnetic substrate 失效
标题翻译：磁存储器件和磁性基片
公开(公告)号：US06741495B2
公开(公告)日：2004-05-25
申请号：US10424086
申请日：2003-04-28
申请人： Tatsuya Kunikiyo , Katsumi Eikyu , Shigenobu Maeda
发明人： Tatsuya Kunikiyo , Katsumi Eikyu , Shigenobu Maeda
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/15 , G11C11/16 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2924/01019 , H01L2924/01021 , H01L2924/01025 , H01L2924/01039 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.
摘要翻译：多个字线（WL1）彼此并联设置，并且多个位线（BL1）彼此平行地设置，与上述字线（WL1）相交。在字线和它们之间的位线的交点处形成MRAM单元（MC2）。提供MRAM单元（MC3），使得由箭头表示的容易轴相对于位线和字线具有45度的角度。因此，实现了能够切换写入功耗的MRAM，并且还实现了能够减少擦除和写入操作所需的时间的MRAM。

8. 发明授权

US06567299B2 Magnetic memory device and magnetic substrate 失效
公开(公告)号：US06567299B2
公开(公告)日：2003-05-20
申请号：US09989155
申请日：2001-11-21
申请人： Tatsuya Kunikiyo , Katsumi Eikyu , Shigenobu Maeda
发明人： Tatsuya Kunikiyo , Katsumi Eikyu , Shigenobu Maeda
IPC分类号： G11C1115
CPC分类号： B82Y10/00 , G11C11/15 , G11C11/16 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2924/01019 , H01L2924/01021 , H01L2924/01025 , H01L2924/01039 , H01L2924/01057 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.

9. 发明授权

US06465335B1 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06465335B1
公开(公告)日：2002-10-15
申请号：US09690836
申请日：2000-10-18
申请人： Tatsuya Kunikiyo
发明人： Tatsuya Kunikiyo
IPC分类号： H01L214763
CPC分类号： H01L21/28247 , H01L21/2807 , H01L21/28518 , H01L29/4966
摘要： A silicon oxide film and a doped polysilicon film are successively formed on a silicon substrate. Then, a doped polysilicon-germanium film is formed on the doped polysilicon film as a film having a higher impurity activation rate than polysilicon. Then, a barrier film, a metal film and another barrier film are successively formed on the doped polysilicon-germanium film. Thus obtained is a method of manufacturing a semiconductor device comprising a polymetal gate capable of suppressing increase of gate resistance also when an impurity introduced into a semiconductor film diffuses into the barrier films.
摘要翻译：在硅衬底上依次形成氧化硅膜和掺杂多晶硅膜。然后，在掺杂多晶硅膜上形成掺杂多晶硅 - 锗膜作为具有比多晶硅更高的杂质活化速率的膜。然后，在掺杂多晶硅 - 锗膜上依次形成阻挡膜，金属膜和另一阻挡膜。这样获得的是一种制造半导体器件的方法，该半导体器件包括能够在导入半导体膜的杂质扩散到阻挡膜中时能够抑制栅极电阻增大的多金属栅极。

10. 发明授权

US06222217B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06222217B1
公开(公告)日：2001-04-24
申请号：US09138568
申请日：1998-08-24
申请人： Tatsuya Kunikiyo
发明人： Tatsuya Kunikiyo
IPC分类号： H01L27108
CPC分类号： H01L27/10855 , H01L21/28525 , H01L27/10814 , H01L27/10873 , H01L27/10888 , H01L28/91 , H01L29/1608 , H01L29/41766
摘要： A semiconductor device capable of restraining a leakage current at an n-p junction of source/drain regions and a manufacturing method of the semiconductor device. A trench is formed in the source/drain regions, a main surface of the source/drain regions is removed at a time of forming the trench and a surface area of the source/drain regions is increased as compared with that before forming the trench. In this manner, a stress per unit area concentrated on the source/drain regions in the vicinity of ends of an isolating oxide film is reduced, and any occurrence of minute defects is restrained. As a result, leakage current caused by any minute defects due to the stress is reduced, and a refresh pause time is prolonged, and in other words, characteristics of a refresh operation can be improved.
摘要翻译：能够抑制源极/漏极区域的n-p结处的漏电流的半导体器件和半导体器件的制造方法。在源极/漏极区域中形成沟槽，在形成沟槽时去除源极/漏极区域的主表面，并且与形成沟槽之前相比源极/漏极区域的表面积增加。以这种方式，减小了在隔离氧化膜的端部附近的源极/漏极区域上集中的每单位面积的应力，并且抑制了任何微小缺陷的发生。结果，由于应力引起的任何微小缺陷引起的泄漏电流减小，并且刷新暂停时间延长，换句话说，可以提高刷新操作的特性。

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