专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07221198B2 Interface circuit and a clock output method therefor 有权
标题翻译：接口电路及其时钟输出方法
公开(公告)号：US07221198B2
公开(公告)日：2007-05-22
申请号：US10943141
申请日：2004-09-17
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
IPC分类号： H03L7/00 , G06F1/04
CPC分类号： G06F1/04
摘要： An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.
摘要翻译：接口电路，响应于控制信号从一个电平变化到另一个电平，输出时钟信号和数据到数据寄存器，该数据寄存器与时钟信号同步地读取数据，以输出时钟信号和数据。接口电路包括时钟输出电路，当控制信号从一个电平变化到另一个电平时，该时钟输出电路响应于时钟信号的电平，将与数据位数相同的时钟信号的时钟输出到数据寄存器。

2. 发明申请

US20050129098A1 Interface circuit and a clock output method therefor 有权
标题翻译：接口电路及其时钟输出方法
公开(公告)号：US20050129098A1
公开(公告)日：2005-06-16
申请号：US10943141
申请日：2004-09-17
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
IPC分类号： H04L7/04 , G06F1/04 , H04L7/00 , H04L12/02 , H04L12/40 , H04B1/38
CPC分类号： G06F1/04
摘要： An interface circuit which outputs a clock signal and data to a data register that serially reads in the data synchronously with the clock signal, in response to a control signal changing from one level to the other level, for outputting the clock signal and the data. The interface circuit comprises a clock output circuit that, responding to the level of the clock signal when the control signal changes from the one level to the other level, outputs clocks of the clock signal that are the same in number as bits of the data to the data register.
摘要翻译：接口电路，响应于控制信号从一个电平变化到另一个电平，输出时钟信号和数据到数据寄存器，该数据寄存器与时钟信号同步地读取数据，以输出时钟信号和数据。接口电路包括时钟输出电路，当控制信号从一个电平变化到另一个电平时，该时钟输出电路响应于时钟信号的电平，将与数据位数相同的时钟信号的时钟输出到数据寄存器。

3. 发明授权

US07724060B2 Interface circuit and a clock output method therefor 有权
标题翻译：接口电路及其时钟输出方法
公开(公告)号：US07724060B2
公开(公告)日：2010-05-25
申请号：US11736913
申请日：2007-04-18
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
IPC分类号： G05F1/04 , H03K3/00
CPC分类号： G06F1/04
摘要： An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
摘要翻译：一个接口电路，响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化，输出时钟信号和数据到数据寄存器，配置为与时钟信号同步地串行读取数据逻辑电平，所述接口电路包括时钟输出电路，所述时钟输出电路被配置为：当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时，检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时，将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时，在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。

4. 发明申请

US20070241797A1 Interface Circuit and a Clock Output Method Therefor 有权
标题翻译：接口电路及其时钟输出方法
公开(公告)号：US20070241797A1
公开(公告)日：2007-10-18
申请号：US11736913
申请日：2007-04-18
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino
IPC分类号： H03L7/00
CPC分类号： G06F1/04
摘要： An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
摘要翻译：一个接口电路，响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化，输出时钟信号和数据到数据寄存器，配置为与时钟信号同步地串行读取数据逻辑电平，所述接口电路包括时钟输出电路，所述时钟输出电路被配置为：当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时，检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时，将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时，在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。

5. 发明授权

US06633271B1 Integrated circuit for driving liquid crystal 有权
标题翻译：用于驱动液晶的集成电路
公开(公告)号：US06633271B1
公开(公告)日：2003-10-14
申请号：US09455856
申请日：1999-12-07
申请人： Shuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
发明人： Shuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
IPC分类号： G09G336
CPC分类号： G09G3/3696 , G09G2320/0606 , G09G2320/066
摘要： A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. Transmission gates TG0-TG10 are provided at respective connection points of twelve resistor elements connected in series between a power supply and the ground. One of the voltages V0-V10 derived from the transmission gates TG0-TG10 in accordance with control signals CA0-CA10 is applied to an operational amplifier 8, and used as a reference voltage VLCD0. The control signals CA0-CA10 are obtained by decoding control data D0-D3 supplied from an external source by a decoder 19. Therefore, the reference voltage VLCD0 can be set in a plurality of stages simply by changing control data D0-D3 to a user specified value. As the twelve resistor elements connected in series are formed on the same semiconductor substrate, display contrast can be adjusted without requiring any external components attached to a liquid crystal driving integrated circuit 1.
摘要翻译：一种液晶驱动集成电路，能够调节显示对比度并且不需要外部连接的部件。传输门TG 0 -TG 10 分别连接在电源和地面。从传输门TG 0导出的电压V 0 -V 10 根据控制信号CA 0 -CA 10 > -TG 应用于运算放大器 8，，并用作参考电压VLCD 0 。通过解码控制数据D 0 获得控制信号CA 0 -CA 10 由解码器从外部源提供的BOLD> -D 3 。因此，通过改变控制数据D 0 ，可以在多个阶段中设置参考电压VLCD 0 BOLD> -D 3 到用户指定的值。由于串联连接的十二个电阻元件形成在相同的半导体基板上，所以可以调节显示对比度，而不需要任何外部元件连接到液晶驱动集成电路 1。

6. 发明授权

US06653999B2 Integrated circuit for driving liquid crystal 有权
标题翻译：用于驱动液晶的集成电路
公开(公告)号：US06653999B2
公开(公告)日：2003-11-25
申请号：US09460171
申请日：1999-12-10
申请人： Shuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
发明人： Shuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
IPC分类号： G09G336
CPC分类号： G09G3/3696 , G09G2320/0606 , G09G2320/066
摘要： A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. A resistor formed by four serially connected resistor elements R1 has one end connected to a reference voltage VLCD0 applied from an operational amplifier 8, and the other end connected to an external variable resistor 25 through a terminal 24. Consequently, liquid crystal driving voltages VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4 can be finely adjusted not only by eleven versions of reference voltage VLCD0 in accordance with voltages at respective connection points of twelve serially connected resistor elements, but by changing the resistance of the external variable resistor 25, to thereby provide a liquid crystal driving integrated circuit 1 that can be used for a variety of general purposes. Since only one external variable resistor 25 is required and this resistor is inherently variable, there is no need to consider variation in characteristics.
摘要翻译：一种液晶驱动集成电路，能够调节显示对比度并且不需要外部连接的部件。由四个串联的电阻元件R1形成的电阻器的一端连接到从运算放大器8施加的参考电压VLCD0，另一端通过端子24连接到外部可变电阻器25.因此，液晶驱动电压VLCD0， VLCD1，VLCD2，VLCD3和VLCD4可以根据十二个串联电阻元件的各个连接点处的电压，而是通过改变外部可变电阻器25的电阻，而不仅仅是参考电压VLCD0的十一个版本，从而提供可用于各种通用目的的液晶驱动集成电路1。由于仅需要一个外部可变电阻器25，并且该电阻器是固有的可变的，所以不需要考虑特性的变化。

7. 发明授权

US5938746A System for prioritizing slave input register to receive data transmission via bi-directional data line from master 失效
标题翻译：用于优先从属输入寄存器的系统，用于通过双向数据线从主机接收数据传输
公开(公告)号：US5938746A
公开(公告)日：1999-08-17
申请号：US805682
申请日：1997-02-25
申请人： Toshiyuki Ozawa , Shuji Motegi , Tetsuya Tokunaga
发明人： Toshiyuki Ozawa , Shuji Motegi , Tetsuya Tokunaga
IPC分类号： G06F13/38 , G06F13/42 , G06F13/18
CPC分类号： G06F13/423
摘要： A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.
摘要翻译：主机（1）和从机（3）经由用于发送时钟CL的传输线（5）连接; 用于双向发送数据DT的另一传输线（6）; 以及用于发送控制信号CE的又一传输线（7）。将控制信号CE转换为“L”后，主机（1）将地址码作为数据DT发送到从机（3）。参照发送的地址码的内容，从机（3）检测是否是从主机（1）到从机（3）的数据传输，反之亦然。当控制信号CE保持“H”时，发生数据传输。从总线驱动器（22）管理从从机（3）到数据线（6）的数据输出。在从时钟CL变为“H”到数据传输之后的控制信号CE变为“L”的期间，总线驱动器（22）被关闭，从而不会对来自主机（1）的数据传输产生不利影响。

8. 发明授权

US5674061A Scroll compression having a discharge muffler chamber 失效
标题翻译：具有放电消声器室的涡旋压缩
公开(公告)号：US5674061A
公开(公告)日：1997-10-07
申请号：US536161
申请日：1995-09-29
申请人： Shuji Motegi , Toshiyuki Nakamura , Fumiaki Sano , Masayuki Kakuda , Kiyoharu Ikeda , Yoshihide Ogawa , Eiji Watanabe , Shinji Nakashima
发明人： Shuji Motegi , Toshiyuki Nakamura , Fumiaki Sano , Masayuki Kakuda , Kiyoharu Ikeda , Yoshihide Ogawa , Eiji Watanabe , Shinji Nakashima
IPC分类号： F04C29/12 , F04C18/02 , F04C23/00 , F04C28/00 , F04C29/00 , F04C29/06 , F04C18/04
CPC分类号： F04C29/12 , F04C18/0215 , F04C18/0253 , F04C29/0035 , F04C29/061 , F04C29/068 , F04C2250/102 , F04C2270/72 , F04C23/008
摘要： The invention concerns a scroll compressor which is low in noise caused by water hammering of a refrigerant gas just after a discharge valve is closed. The scroll compressor includes a discharge member (45) having a discharge port (8) opposed to a discharge port (5) of a fixed scroll (2) and a discharge valve (9) opposed to the discharge port (8) of the discharge member (45) and opened/closed depending on a difference between flow passage pressure of a refrigerant gas and pressure in a high pressure space (27) in a sealed vessel (1). At least either of the fixed scroll (2) and the discharge member (45) is formed with a muffler chamber communicated with the discharge port (5, 8) and having a diameter larger than a diameter of the discharge port (5) of the fixed scroll (2) for suppressing occurrence of an impulse wave caused by water hammering when the discharge valve (9) is closed. Noise caused by a pressure ripple of the discharge port lessens, quieting the operation of the scroll compressor.
摘要翻译：本发明涉及一种涡旋式压缩机，该涡旋式压缩机在排放阀关闭之后由于致冷剂气体的水锤而引起的噪音低。涡旋压缩机包括排出构件（45），其具有与固定涡旋件（2）的排出口（5）相对的排出口（8）和与排出口的排出口（8）相对的排出阀（9）构件（45），并且根据制冷剂气体的流路压力与密封容器（1）中的高压空间（27）中的压力之间的差异来打开/关闭。固定涡旋件（2）和排出构件（45）中的至少一个形成有与排出口（5,8）连通并且具有大于排出口（5）的排出口（5）的直径的消声器室固定涡旋盘（2），用于在排出阀（9）关闭时抑制由水击引起的脉冲波的发生。由排气口的压力波动引起的噪音降低，使涡旋压缩机的运转静止。

9. 发明授权

US5800142A Scroll compressor having a counterboring part communicating with an intermediate pressure chamber 失效
标题翻译：涡旋压缩机具有与中间压力室连通的对置部分
公开(公告)号：US5800142A
公开(公告)日：1998-09-01
申请号：US670224
申请日：1996-06-21
申请人： Shuji Motegi , Toshiyuki Nakamura , Fumiaki Sano , Masayuki Kakuda , Kiyoharu Ikeda , Yoshihide Ogawa , Eiji Watanabe , Shinji Nakashima
发明人： Shuji Motegi , Toshiyuki Nakamura , Fumiaki Sano , Masayuki Kakuda , Kiyoharu Ikeda , Yoshihide Ogawa , Eiji Watanabe , Shinji Nakashima
IPC分类号： F04C29/12 , F04C18/02 , F04C23/00 , F04C28/00 , F04C29/00 , F04C29/06 , F04C18/04
CPC分类号： F04C29/12 , F04C18/0215 , F04C18/0253 , F04C29/0035 , F04C29/061 , F04C29/068 , F04C2250/102 , F04C2270/72 , F04C23/008
摘要： The invention concerns a scroll compressor which is low in noise caused by water hammering of a refrigerant gas just after a discharge valve is closed. The scroll compressor includes a discharge member (45) having a discharge port (8) opposed to a discharge port (5) of a fixed scroll (2) and a discharge valve (9) opposed to the discharge port (8) of the discharge member (45) and opened/closed depending on a difference between flow passage pressure of a refrigerant gas and pressure in a high pressure space (27) in a sealed vessel (1). At least either of the fixed scroll (2) and the discharge member (45) is formed with a counterboring part which communicates with an intermediate pressure chamber after the high and intermediate pressure chambers have begun to communicate via separation of the spiral teeth.
摘要翻译：本发明涉及一种涡旋式压缩机，该涡旋式压缩机在排放阀关闭之后由于致冷剂气体的水锤而引起的噪音低。涡旋压缩机包括排出构件（45），其具有与固定涡旋件（2）的排出口（5）相对的排出口（8）和与排出口的排出口（8）相对的排出阀（9）构件（45），并且根据制冷剂气体的流路压力与密封容器（1）中的高压空间（27）中的压力之间的差异来打开/关闭。固定涡旋件（2）和排出构件（45）中的至少一个形成有在通过螺旋齿的分离开始高压和中压室已经开始连通之后与中间压力室连通的对中部分。

10. 发明授权

US5846065A Scroll compressor with axial biasing 失效
标题翻译：带轴向偏压的涡旋压缩机
公开(公告)号：US5846065A
公开(公告)日：1998-12-08
申请号：US882216
申请日：1997-06-25
申请人： Fumiaki Sano , Masayuki Kakuda , Hiroshi Ogawa , Kiyoharu Ikeda , Yoshihide Ogawa , Eiji Watanabe , Toshiyuki Nakamura , Shuji Motegi , Norihide Kobayashi
发明人： Fumiaki Sano , Masayuki Kakuda , Hiroshi Ogawa , Kiyoharu Ikeda , Yoshihide Ogawa , Eiji Watanabe , Toshiyuki Nakamura , Shuji Motegi , Norihide Kobayashi
IPC分类号： F01C17/06 , F04C18/02 , F04C23/00 , F04C27/00 , F04C28/26 , F01C1/04
CPC分类号： F04C18/0215 , F01C17/066 , F04C23/008 , F04C27/005 , F04C2230/60 , F04C28/265 , F05B2230/60
摘要： The invention concerns a high-reliability scroll compressor with little moment for making a fixed scroll unstable. A scroll compressor comprising in a sealed vessel a fixed scroll, an orbiting scroll being combined with the fixed scroll for forming a compression space, and executing orbiting motion with respect to the fixed scroll, a frame for axially supporting the orbiting scroll and radially supporting a drive shaft, and a seal member being disposed in an axial gap between a high and low pressure separator stuck to the frame by any method and the fixed scroll, wherein a base plate outer peripheral surface of the fixed scroll is radially supported by a stationary member coaxial with the base plate outer peripheral surface, and wherein with the stationary member as a guide, the fixed scroll can make axial movement within a range in which it interferes with the orbiting scroll downward in the axial direction and with the high and low pressure separator upward in the axial direction.
摘要翻译：本发明涉及一种高可靠性的涡旋压缩机，其具有用于使固定涡旋不稳定的小时刻。一种涡旋式压缩机，包括在密封容器中的固定涡旋件，与固定涡旋件组合以形成压缩空间并且相对于固定涡旋件执行轨道运动的动涡旋盘，用于轴向支撑绕动涡盘并径向支撑驱动轴和密封部件，其通过任何方法和固定涡旋件布置在粘附在框架上的高压分离器和低压分离器之间的轴向间隙中，其中固定涡旋盘的基板外周面由静止部件与基板外周表面同轴，并且其中固定构件作为引导件，固定涡旋件可以在与轴向方向下向下的绕动涡卷干涉的范围内以及高低压分离器在轴向上向上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式