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1. 发明申请

US20220342202A1 CIRCUITS AND METHODS TO CALIBRATE MIRROR DISPLACEMENT 有权
公开(公告)号：US20220342202A1
公开(公告)日：2022-10-27
申请号：US17240483
申请日：2021-04-26
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Robert Floyd Payne , James Norman Hall
IPC分类号： G02B26/08 , G01B7/06
摘要： A calibration circuit providing a programmable voltage generator that is selectively connectable to a first capacitor plate of a capacitive structure to supply a voltage thereto. A reference voltage generator is coupled to the output of the programmable voltage generator and generates a reference voltage. A comparator receives the reference voltage and a discharging voltage from the capacitive structure during a discharge period and, based on those inputs, generates a signal that is output to a digital controller. A constant current source is selectively connectable to the capacitive structure to generate a constant current. Based on the output of the comparator, the constant current, and a count representing a time during which the discharging voltage decreases, the digital controller measures capacitance to calibrate a movable mirror of the capacitive structure. During calibration, the digital controller controls the programmable voltage generator and a second capacitor plate of the capacitive structure.

2. 发明申请

US20210065830A1 TRACK AND HOLD CIRCUITS WITH TRANSFORMER COUPLED BOOTSTRAP SWITCH 有权
公开(公告)号：US20210065830A1
公开(公告)日：2021-03-04
申请号：US17003185
申请日：2020-08-26
申请人： Texas Instruments Incorporated
发明人： Ashwin Raghunathan , Marco Corsi , Baher Haroun , Seyed Miaad Seyed Aliroteh , Swaminathan Sankaran , Robert Floyd Payne
IPC分类号： G11C27/02 , H03M1/06 , H03M1/12
摘要： A track and hold circuit includes a signal input terminal, a clock input terminal, an output terminal, a transistor, and a bootstrapping circuit with a transformer. The transistor includes a source, a drain, and a gate, where the source is coupled to the signal input terminal, and the drain is coupled to the output terminal. The transformer includes a primary winding coupled to the clock input terminal, and a secondary winding. The secondary winding is coupled between the source and the gate to control a gate-source voltage of the transistor.

3. 发明授权

US10483609B2 Dielectric waveguide having a core and cladding formed in a flexible multi-layer substrate 有权
公开(公告)号：US10483609B2
公开(公告)日：2019-11-19
申请号：US15614969
申请日：2017-06-06
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Robert Floyd Payne , Gerd Schuppener , Juan Alejandro Herbsommer
IPC分类号： H01P3/16 , H01P11/00
摘要： A digital system has a dielectric core waveguide that is formed within a multilayer substrate. The dielectric waveguide has a longitudinal dielectric core member formed in the core layer having two adjacent longitudinal sides each separated from the core layer by a corresponding slot portion formed in the core layer The dielectric core member has the first dielectric constant value. A cladding surrounds the dielectric core member formed by a top layer and the bottom layer infilling the slot portions of the core layer. The cladding has a dielectric constant value that is lower than the first dielectric constant value.

4. 发明申请

US20180309431A1 DIGITAL CLOCK-DUTY-CYCLE CORRECTION 审中-公开
公开(公告)号：US20180309431A1
公开(公告)日：2018-10-25
申请号：US16023643
申请日：2018-06-29
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mohammad Elbadry , Robert Floyd Payne , Gerd Schuppener
IPC分类号： H03K5/156 , H02M3/07
CPC分类号： H03K5/1565 , H02M3/07
摘要： A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

5. 发明申请

US20170192449A1 EMBEDDED CLOCK IN A COMMUNICATION SYSTEM 有权
公开(公告)号：US20170192449A1
公开(公告)日：2017-07-06
申请号：US14983776
申请日：2015-12-30
申请人： Texas Instruments Incorporated
发明人： Robert Floyd Payne
IPC分类号： G06F1/04 , H04B1/04 , H04B1/16
CPC分类号： G06F1/04 , H04B1/04 , H04B1/16 , H04L25/4904
摘要： A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.

6. 发明申请

US20160072173A1 COUPLER TO LAUNCH ELECTROMAGNETIC SIGNAL FROM MICROSTRIP TO DIELECTRIC WAVEGUIDE 审中-公开
标题翻译：从微电极到电介质波导发射电磁信号的耦合器
公开(公告)号：US20160072173A1
公开(公告)日：2016-03-10
申请号：US14939128
申请日：2015-11-12
申请人： Texas Instruments Incorporated
发明人： Juan Alejandro Herbsommer , Robert Floyd Payne , Gerd Schuppener , Baher Haroun
IPC分类号： H01P3/16 , H01P5/18
CPC分类号： H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
摘要： A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.
摘要翻译：金属波导安装在多层基板上。金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到接触多层基板。锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。

7. 发明授权

US08891717B1 Method and system for comparing digital values 有权
标题翻译：比较数字值的方法和系统
公开(公告)号：US08891717B1
公开(公告)日：2014-11-18
申请号：US13954424
申请日：2013-07-30
申请人： Texas Instruments Incorporated
发明人： Robert Floyd Payne
IPC分类号： H03D3/24 , H04L7/00
CPC分类号： H04L7/033 , H03L7/00
摘要： One bit is a smallest increment of binary measurement in first and second digital values. The first digital value is converted into a first analog signal. The second digital value is converted into a second analog signal. The first analog signal is augmented by a first amount that equates to less than the smallest increment of binary measurement, so that the augmented first analog signal by definition does not equal the second analog signal. The second analog signal is augmented by a second amount that equates to less than the smallest increment of binary measurement, so that the augmented second analog signal by definition does not equal the first analog signal. The augmented first analog signal is compared to the second analog signal, and a first signal is output in response thereto. The augmented second analog signal is compared to the first analog signal, and a second signal is output in response thereto. In response to the first and second signals, a determination is made about whether the first digital value is greater than the second digital value, whether the first digital value is less than the second digital value, and whether the first digital value is equal to the second digital value.
摘要翻译：一位是第一和第二数字值中二进制测量的最小增量。第一数字值被转换成第一模拟信号。第二数字值被转换成第二模拟信号。第一模拟信号被增加等于小于二进制测量的最小增量的第一量，使得通过定义的增强的第一模拟信号不等于第二模拟信号。第二模拟信号被增加等于小于二进制测量的最小增量的第二量，使得通过定义的增强的第二模拟信号不等于第一模拟信号。将增大的第一模拟信号与第二模拟信号进行比较，并响应于此输出第一信号。将增大的第二模拟信号与第一模拟信号进行比较，并响应于此输出第二信号。响应于第一和第二信号，确定第一数字值是否大于第二数字值，第一数字值是否小于第二数字值，以及第一数字值是否等于第二数字值第二数字值。

8. 发明申请

US20140285291A1 Dielectric Waveguide with Multiple Channels 有权
标题翻译：多通道介质波导
公开(公告)号：US20140285291A1
公开(公告)日：2014-09-25
申请号：US13854959
申请日：2013-04-02
申请人： Texas Instruments Incorporated
发明人： Robert Floyd Payne , Juan Alejandro Herbsommer , Gerd Schuppener
IPC分类号： H01P3/16 , H01P11/00
CPC分类号： H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
摘要： A multichannel dielectric wave guide includes a set of dielectric core members that have a length and a cross section shape that is approximately rectangular, The core members have a first dielectric constant value. A cladding surrounds the set of dielectric core members and has a second dielectric constant value that is lower than the first dielectric constant.
摘要翻译：多通道介电波导包括一组具有近似矩形的长度和截面形状的介质芯构件。芯构件具有第一介电常数值。包层围绕该组介电芯构件并且具有低于第一介电常数的第二介电常数值。

9. 发明申请

US20140285281A1 Coupler to Launch Electromagnetic Signal from Microstrip to Dielectric Waveguide 有权
标题翻译：耦合器从微带到介质波导发射电磁信号
公开(公告)号：US20140285281A1
公开(公告)日：2014-09-25
申请号：US13854947
申请日：2013-04-01
申请人： Texas Instruments Incorporated
发明人： Juan Alejandro Herbsommer , Robert Floyd Payne , Gerd Schuppener , Baher Haroun
IPC分类号： H01P5/107
CPC分类号： H01P3/16 , G02B6/4416 , H01L2223/6677 , H01L2224/16227 , H01L2224/73204 , H01L2924/15192 , H01L2924/15311 , H01P3/121 , H01P3/165 , H01P5/00 , H01P5/087 , H01P5/107 , H01P5/184 , H01P11/001 , H01P11/002 , H01Q1/50 , H01Q19/108 , H01Q19/30 , H04B1/40 , Y10T29/49016 , Y10T29/49826
摘要： A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.
摘要翻译：金属波导安装在多层基板上。金属波导具有由顶部，底部和侧面形成的开口端，该开口端被配置为容纳电介质波导的芯构件，并且相反的锥形端通过使金属波导的顶部通过金属波导的底部下降到接触多层基板。锥形末端的顶点耦合到接地平面元件，并且金属波导的底侧与多人基板接触并耦合到微带线。

10. 发明申请

US20230025757A1 SELF-CALIBRATING ON-OFF KEYING BASED DIGITAL ISOLATOR 有权
公开(公告)号：US20230025757A1
公开(公告)日：2023-01-26
申请号：US17489483
申请日：2021-09-29
申请人： Texas Instruments Incorporated
发明人： RR Manikandan , Kumar Anurag Shrivastava , Robert Floyd Payne , Anant Shankar Kamath , Swaminathan Sankaran , Kishalay Datta , Siraj Akhtar , Mark Edward Wentroble , Suvadip Banerjee , Rakesh Hariharan , Gurumurti Kailaschandra Avhad
IPC分类号： H04B1/44 , H03K3/017 , H03K5/24 , H04L27/04 , H04L27/06
摘要： In described examples, an integrated circuit includes an on-off keying (OOK) digital isolator, which includes a first circuitry, a multiplexer, an OOK modulator, an isolation barrier, an OOK envelope detector, and a second circuitry. The first circuitry generates and outputs a calibration signal. The multiplexer has a data signal input, and an input coupled to a first circuitry output. An OOK modulator input is coupled to a multiplexer output. An isolation barrier input is coupled to an OOK modulator output. An OOK envelope detector input is coupled to an isolation barrier output. The second circuitry includes an input coupled to an OOK envelope detector output, and an output coupled to an OOK envelope detector control input. The second circuitry detects a duty cycle distortion (DCD) of the OOK envelope detector output, and outputs a control signal to change the OOK envelope detector output's duty cycle based on the detected DCD.

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