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1. 发明申请

US20170099711A1 Transmitter Architecture for Photoplethysmography Systems 审中-公开
公开(公告)号：US20170099711A1
公开(公告)日：2017-04-06
申请号：US15131831
申请日：2016-04-18
申请人： Texas Instruments Incorporated
发明人： Arup Polley , Ajit Sharma , Srinath Ramaswamy , Sriram Narayanan
IPC分类号： H05B33/08 , A61B5/1455 , A61B5/024
CPC分类号： H05B33/0818 , A61B5/02427 , A61B5/14551 , A61B5/7225 , Y02B20/346
摘要： An LED (light-emitting diode) driver for a photoplethysmography system, including a switched-mode operational amplifier for driving a driver transistor with a source-drain path in series with the LED. In a first clock phase in which the LED is disconnected from the driver transistor, the amplifier is coupled in unity gain mode, and a sampling capacitor stores a voltage corresponding to the offset and flicker noise of the amplifier; the gate of the driver transistor is precharged to a reference voltage in this first clock phase. In a second clock phase, the sampled voltage at the capacitor is subtracted from the reference voltage applied to the amplifier input, so that the LED drive is adjusted according to the sampled noise. A signal from the transmitter channel is forwarded to a noise/ripple remover in the receiving channel, to remove transmitter noise from the received signal.

2. 发明授权

US09599975B2 Sensor synchronized networks using overlapping sensor fields 有权
公开(公告)号：US09599975B2
公开(公告)日：2017-03-21
申请号：US14278661
申请日：2014-05-15
申请人： Texas Instruments Incorporated
发明人： Leonardo William Estevez , Sriram Narayanan , Gangadhar Burra
IPC分类号： G05B15/02 , H04N7/18 , H04W52/02 , G05B19/05
CPC分类号： G05B15/02 , G05B19/05 , G05B19/054 , G05B2219/1133 , G05B2219/163 , G05B2219/2642 , G05B2219/31251 , H04N7/181 , H04W52/0209 , H04W52/0216 , H04W52/0219 , H04W52/0229 , H04W52/0254 , Y02D70/00
摘要： A method of synchronizing includes providing a sensor network including sensor nodes having object recognition sensors (ORS's) and building automation network nodes. The ORS's have partially overlapping fields of view in a sensed overlap area in the building. Movement of an individual through the sensed overlap area triggers dynamic synchronizing with the first sensor node waking up and sending a first RF request to join a subnet and for a schedule of wakeup times, the first sensor node receiving a response from any sensor node that receives the first request including synchronization information having times the first sensor node should wake up. The second sensor node is activated by the individual's movement and sends a second RF message to join the subnet and for a schedule of wakeup times. The first sensor node receives the second RF message and in response sends the synchronization information to the second sensor node.

3. 发明申请

US20160109261A1 SENSOR POWER MANAGEMENT 审中-公开
标题翻译：传感器电源管理
公开(公告)号：US20160109261A1
公开(公告)日：2016-04-21
申请号：US14981894
申请日：2015-12-28
申请人： Texas Instruments Incorporated
发明人： Sriram Narayanan , David Louis Freeman , Marco Corsi
IPC分类号： G01D3/10 , G01D18/00
CPC分类号： G01D3/10 , G01D18/00
摘要： A sensor power management arrangement includes a signal processing circuit configured to receive signal from a sensor, to test the signal against at least one criterion, and to pass the signal for further processing in response to the signal passing the at least one criterion. In this way, only signals that are of a sufficient importance or significance will consume the maximum amount of processing energy and through processing by later processes or circuitry. Should a signal from a sensor not be strong enough or meet other criteria, power will not be wasted in preparing that signal for provision to the microcontroller or microprocessor. Additional flexibility in the sensor power management can be realized by adjusting the criteria against which the sensor signal is compared based on a status of the sensor apparatus.
摘要翻译：传感器电源管理装置包括信号处理电路，其被配置为从传感器接收信号，以针对至少一个准则测试信号，并且响应于通过所述至少一个准则的信号而传递用于进一步处理的信号。以这种方式，仅具有足够重要性或重要性的信号将消耗最大量的处理能量并且通过后续处理或电路的处理。如果来自传感器的信号不够牢固或符合其他标准，则在准备将信号提供给微控制器或微处理器时，功率不会被浪费。基于传感器装置的状态，可以通过调整传感器信号进行比较的标准来实现传感器功率管理中的额外的灵活性。

4. 发明授权

US09148159B1 Dual comparator-based error correction scheme for analog-to-digital converters 有权
标题翻译：用于模数转换器的基于双比较器的纠错方案
公开(公告)号：US09148159B1
公开(公告)日：2015-09-29
申请号：US14209813
申请日：2014-03-13
申请人： Texas Instruments Incorporated
发明人： Ajit Sharma , Seung Bae Lee , Srinath M. Ramaswamy , Sriram Narayanan , Arup Polley
IPC分类号： H03M1/06 , H03M1/12 , H03M1/36 , H03M1/44 , H03M1/00
CPC分类号： H03M1/0678 , H03M1/00 , H03M1/12 , H03M1/468
摘要： An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
摘要翻译：模数转换器（ADC）包括第一比较器，第二比较器和判定定时比较逻辑单元。第一比较器被配置为输出第一输出电压，并且第二比较器被配置为在ADC的相同的二进制算法迭代期间输出第二输出电压。所述判定定时比较逻辑单元被配置为识别所述第一输出电压的第一极性和所述第二输出电压的第二极性，并且如果所述第一极性等于第二极性，则将至少一个冗余电容器插入下一个 ADC的二进制算法迭代。

5. 发明申请

US20150263744A1 DUAL COMPARATOR-BASED ERROR CORRECTION SCHEME FOR ANALOG-TO-DIGITAL CONVERTERS 有权
标题翻译：用于模拟数字转换器的双基于比较器的错误校正方案
公开(公告)号：US20150263744A1
公开(公告)日：2015-09-17
申请号：US14209813
申请日：2014-03-13
申请人： Texas Instruments Incorporated
发明人： Ajit Sharma , Seung Bae Lee , Srinath M. Ramaswamy , Sriram Narayanan , Arup Polley
IPC分类号： H03M1/06 , H03M1/36 , H03M1/44 , H03M1/12
CPC分类号： H03M1/0678 , H03M1/00 , H03M1/12 , H03M1/468
摘要： An analog-to-digital converter (ADC) includes a first comparator, a second comparator, and a decision timing comparison logic unit. The first comparator is configured to output a first output voltage and the second comparator is configured to output a second output voltage during a same binary algorithmic iteration of the ADC. The decision timing comparison logic unit is configured to identify a first polarity of the first output voltage and a second polarity of the second output voltage and, if the first polarity is equivalent to a second polarity, to insert at least one redundant capacitor for a next binary algorithmic iteration of the ADC.
摘要翻译：模数转换器（ADC）包括第一比较器，第二比较器和判定定时比较逻辑单元。第一比较器被配置为输出第一输出电压，并且第二比较器被配置为在ADC的相同二进制算法迭代期间输出第二输出电压。所述判定定时比较逻辑单元被配置为识别所述第一输出电压的第一极性和所述第二输出电压的第二极性，并且如果所述第一极性等于第二极性，则将至少一个冗余电容器插入下一个 ADC的二进制算法迭代。

6. 发明申请

US20160380660A1 Methods and Apparatus for Reducing Noise, Power and Settling Time in Multi-Modal Analog Multiplexed Data Acquisition Systems 有权
标题翻译：用于降低多模态模拟多路复用数据采集系统中噪声，功率和稳定时间的方法和装置
公开(公告)号：US20160380660A1
公开(公告)日：2016-12-29
申请号：US15084052
申请日：2016-03-29
申请人： Texas Instruments Incorporated
发明人： Arup Polley , Ajit Sharma , Seung Bae Lee , Sriram Narayanan , Srinath Ramaswamy
IPC分类号： H04B1/10
CPC分类号： H04B1/1036 , H04B1/0028 , H04B2001/1054
摘要： Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.
摘要翻译：在多模式模拟复用数据采集系统中，通过快速建立时间和更高性能降低噪声和功耗。示例性装置配置包括被配置为接收多个模拟输入信号的电路输入; 模数转换器电路，被配置为输出模拟电压的数字表示; 选择电路，被配置为选择在所述电路输入处接收的所述模拟输入信号之一; 耦合以接收所选择的一个模拟输入信号的缓冲器; 滤波器，耦合到所述缓冲器并且被配置为响应于控制信号执行高带宽采样操作和低带宽采样操作并具有滤波器输出; 以及耦合到所述滤波器以对所述滤波器输出进行采样并且具有耦合到所述模数转换器的输出的采样电容器。公开了方法和附加装置布置。

7. 发明授权

US09007244B2 Sampling rate based adaptive analog biasing 有权
标题翻译：基于采样率的自适应模拟偏置
公开(公告)号：US09007244B2
公开(公告)日：2015-04-14
申请号：US14321434
申请日：2014-07-01
申请人： Texas Instruments Incorporated
发明人： Ajit Sharma , Sriram Narayanan , Srinath M. Ramaswamy
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/124 , H03M1/002 , H03M1/1255 , H03M1/126
摘要： A mixed signal device includes an analog circuit and a digital circuit coupled to the analog circuit. The digital circuit includes a component that samples a signal at a sampling rate that is dynamically variable by the digital circuit based on the bandwidth of the incoming signal. The digital circuit is to automatically assert a signal to the analog circuit to change a bias current of the analog circuit based on a change to the sampling rate in the digital circuit.
摘要翻译：混合信号装置包括模拟电路和耦合到模拟电路的数字电路。数字电路包括以基于输入信号的带宽由数字电路动态变化的采样率对信号进行采样的部件。数字电路是根据数字电路中采样率的变化，自动向模拟电路断言信号以改变模拟电路的偏置电流。

8. 发明授权

US09721349B2 Method and system for automatically counting physical objects within a periphery band and an excluded region 有权
公开(公告)号：US09721349B2
公开(公告)日：2017-08-01
申请号：US14189151
申请日：2014-02-25
申请人： Texas Instruments Incorporated
发明人： Sriram Narayanan , Russell Rosenquist , Srinath Ramaswamy
IPC分类号： G06K9/00 , G06T7/20 , G06T7/73 , G08B13/18
CPC分类号： G06T7/20 , G06K9/00771 , G06T7/73 , G06T2207/10048 , G06T2207/30242 , G08B13/18
摘要： A periphery band is around an excluded region. For automatically counting physical objects within the periphery band and the excluded region, an imaging sensor captures: a first image of the periphery band and the excluded region; and a second image of the periphery band and the excluded region. In response to the first image, a first number is counted of physical objects within the periphery band and the excluded region. Relevant motion is automatically detected within the periphery band, while ignoring motion within the excluded region. In response to the second image, a second number is counted of physical objects within the periphery band and the excluded region. In response to determining that a discrepancy exists between the detected relevant motion and the second number, the discrepancy is handled.

9. 发明授权

US09397685B1 Sensor with low power model based feature extractor 有权
标题翻译：传感器采用低功耗型功能提取器
公开(公告)号：US09397685B1
公开(公告)日：2016-07-19
申请号：US14806826
申请日：2015-07-23
申请人： Texas Instruments Incorporated
发明人： Sriram Narayanan , Srinath Mathur Ramaswamy , Arup Polley , Ajit Sharma
IPC分类号： H03M1/00 , H03M1/12
CPC分类号： H03M1/1245
摘要： Described examples include low power analog front end circuits for sensing repeating signal waveforms, including a first sampling circuit to sample an input signal, an analog detector circuit to provide a detector output signal representing a feature of the input signal, a second sampling circuit to sample the detector output signal, and a control circuit to control a sample rate or other analog front end operating parameter at least partially according to the sampled detector output signal, and to selectively enable and disable the analog detector circuit at least partially according to a model representing an expected repeating waveform of the input signal.
摘要翻译：所描述的示例包括用于感测重复信号波形的低功率模拟前端电路，包括用于对输入信号进行采样的第一采样电路，模拟检测器电路，以提供表示输入信号特征的检测器输出信号，第二采样电路检测器输出信号，以及控制电路，用于至少部分地根据采样的检测器输出信号来控制采样率或其他模拟前端工作参数，并且至少部分地根据代表的模型来选择性地启用和禁用模拟检测器电路预期的输入信号的重复波形。

10. 发明授权

US09319059B1 Calibrated SAR ADC having a reduced size 有权
标题翻译：具有减小尺寸的校准SAR ADC
公开(公告)号：US09319059B1
公开(公告)日：2016-04-19
申请号：US14732676
申请日：2015-06-06
申请人： Texas Instruments Incorporated
发明人： Ajit Sharma , Seung Bae Lee , Srinath Mathur Ramaswamy , Sriram Narayanan , Arup Polley
IPC分类号： H03M1/38 , H03M1/46 , H03M1/10 , H03M1/40
CPC分类号： H03M1/46 , H03M1/1057 , H03M1/38 , H03M1/403 , H03M1/468
摘要： The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs−1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.
摘要翻译：基于校准电容器的逐次逼近寄存器（SAR）模数转换器（ADC）（100）的半导体制造所需的硅绝缘体通过使用多个共用电容器（SC1-SCs-1）而大大降低，它们在校准模式下工作时用作校准电容器，在正常模式下工作时用作位电容器。

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