专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11349439B2 Method for amplifier load current cancellation in a current integrator and current integrator with amplifier load current cancellation 有权
公开(公告)号：US11349439B2
公开(公告)日：2022-05-31
申请号：US17041213
申请日：2019-04-23
申请人： ams International AG
发明人： Fridolin Michel
IPC分类号： H03F1/26 , H03M1/40 , H03M3/00
摘要： The amplifier load current cancellation in a current integrator comprises applying an input current to an operational transconductance amplifier provided with an integration capacitor for current integration, leading an output current of the operational transconductance amplifier through a sensing resistor, thus producing a voltage drop over the sensing resistor, generating a cancellation current dependent on the voltage drop over the sensing resistor, and injecting the cancellation current to the output current, before or after the output current passes the sensing resistor, thus eliminating a dependence of the output current on the input current.

2. 发明授权

US11032501B2 Low noise image sensor system with reduced fixed pattern noise 有权
公开(公告)号：US11032501B2
公开(公告)日：2021-06-08
申请号：US16272228
申请日：2019-02-11
申请人： Apple Inc.
发明人： Dusan Stepanovic , Sedigheh Hashemi , Mansour Keramat , Hyunsik Park
IPC分类号： H04N5/365 , H04N5/357 , H04N5/3745 , H04N5/378 , H03M1/06 , H03M1/46 , H03M1/40
摘要： An image sensing system and methods for operating the same are disclosed. An image sensing system includes a plurality of pixel circuits, a multiplexer configured to select one of the pixel circuit and provide analog pixel data without sampling, and a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert the analog pixel data into digital data. The SAR ADC includes a capacitive digital-to-analog converter (CDAC) configured to convert contents of the SAR into a corresponding analog signal for comparison, by a comparator, with the analog pixel data. The CDAC includes a two-dimensional array of circuit elements. A control circuit in the image sensing system is configured to cause random ones of the circuit elements of the CDAC to be selected for generation of the corresponding analog signal and add a dithering signal so a CDAC output and shuffle a multiplexer switch sequence to improve fixed pattern noise.

3. 发明授权

US10541704B2 Pipelined analog-to-digital converter 有权
公开(公告)号：US10541704B2
公开(公告)日：2020-01-21
申请号：US16285537
申请日：2019-02-26
申请人： MEDIATEK INC.
发明人： Tzu-Chien Wu
IPC分类号： H03M1/38 , H03M1/46 , H03M1/16 , H03M1/40 , H03M1/06 , H03M1/80
摘要： A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.

4. 发明申请

US20190305793A1 PIPELINED ANALOG-TO-DIGITAL CONVERTER 审中-公开
公开(公告)号：US20190305793A1
公开(公告)日：2019-10-03
申请号：US16285537
申请日：2019-02-26
申请人： MEDIATEK INC.
发明人： Tzu-Chien WU
IPC分类号： H03M1/46 , H03M1/16 , H03M1/80 , H03M1/06 , H03M1/40
摘要： A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input

5. 发明申请

US20180212615A1 PRECHARGE SWITCH-CAPACITOR CIRCUIT AND METHOD 审中-公开
公开(公告)号：US20180212615A1
公开(公告)日：2018-07-26
申请号：US15927510
申请日：2018-03-21
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Paul STULIK
IPC分类号： H03M1/12 , H03M1/40 , H03M1/08 , H02M3/07 , H03M1/06
CPC分类号： H03M1/124 , H02M3/07 , H03M1/06 , H03M1/0863 , H03M1/403
摘要： An input sampling stage circuit includes, a precharge buffer, a precharge switch-capacitor circuit, and an input sampling capacitor. The precharge buffer is configured to buffer an input voltage. The precharge switch-capacitor circuit includes a plurality of switches, a first capacitor, and a second capacitor configured such that the first and second capacitors are connected in series during a coarse sampling time and in parallel during a fine sampling time and charge transfer time. The input sampling capacitor is configured to sample the input voltage through the precharge switch-capacitor circuit during the coarse sampling time and sample the input voltage directly during the fine sampling time.

6. 发明授权

US09560300B2 Analog to digital converter for solid-state image pickup device 有权
标题翻译：用于固态摄像装置的模数转换器
公开(公告)号：US09560300B2
公开(公告)日：2017-01-31
申请号：US15082913
申请日：2016-03-28
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Hiroto Utsunomiya , Katsumi Dosaka , Hiroshi Kato , Fukashi Morishita , Fumiyasu Sasaki
IPC分类号： H04N5/3745 , H04N5/376 , H03M1/66 , H03M1/40 , H03M1/14 , H04N5/378 , H04N5/374
CPC分类号： H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
摘要翻译：提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。通过垂直读出线输出的像素信号的电位被保持在节点处。多个电容器电容耦合到保持像素信号的节点。通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。此后，开始数字值的低位的转换。因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。

7. 发明授权

US09531400B1 Digitally calibrated successive approximation register analog-to-digital converter 有权
标题翻译：数字校准的逐次逼近寄存器模数转换器
公开(公告)号：US09531400B1
公开(公告)日：2016-12-27
申请号：US14932798
申请日：2015-11-04
申请人： AVNERA CORPORATION
发明人： Jianping Wen , Garry Link , Wai Lee
IPC分类号： H03M1/06 , H03M1/40 , H03M1/44 , H03M1/46
CPC分类号： H03M1/1009 , H03M1/0682 , H03M1/0692 , H03M1/38 , H03M1/403 , H03M1/462 , H03M1/468 , H03M1/804
摘要： A circuit can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the first input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with a common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a first input voltage Vinp, a reference voltage Vref, the common mode voltage Vcm, and ground; a second plurality of capacitors Cn[0:n] that each have a top plate and a bottom plate, wherein each top plate is electrically coupled with the second input of the voltage comparator Vd, wherein each top plate is also switchably electrically coupled with the common mode voltage Vcm, and wherein each bottom plate is switchably electrically coupled between a second input voltage Vinn, the reference voltage Vref, the common mode voltage Vcm, and ground; and a successive approximation register (SAR) controller coupled with the output of the voltage comparator Vd.
摘要翻译：电路可以包括具有第一输入，第二输入和输出的电压比较器Vd; 具有顶板和底板的第一多个电容器Cp [0：n]，其中每个顶板与电压比较器Vd的第一输入电耦合，其中每个顶板也可切换地电耦合到共模电压Vcm，并且其中每个底板可切换地电耦合在第一输入电压Vinp，参考电压Vref，共模电压Vcm和地之间; 分别具有顶板和底板的第二多个电容器Cn [0：n]，其中每个顶板与电压比较器Vd的第二输入电耦合，其中每个顶板也可切换地电耦合到共模电压Vcm，并且其中每个底板可切换地电耦合在第二输入电压Vinn，参考电压Vref，共模电压Vcm和地之间; 以及与电压比较器Vd的输出耦合的逐次逼近寄存器（SAR）控制器。

8. 发明授权

US09385740B2 SAR ADC and method thereof 有权
标题翻译： SAR ADC及其方法
公开(公告)号：US09385740B2
公开(公告)日：2016-07-05
申请号：US14919830
申请日：2015-10-22
申请人： MEDIATEK Inc.
发明人： Chi Yun Wang , Jen-Che Tsai , Shu-Wei Chu
IPC分类号： H03M1/38 , H03M1/46 , H03M1/42 , H03M1/12 , H03M1/08 , H03M1/40
CPC分类号： H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
摘要： A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
摘要翻译：提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。输入开关单元将差分模拟输入信号交替耦合到比较器。正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。

9. 发明授权

US09013345B2 Successive approximation AD converter and successive approximation AD conversion method 有权
标题翻译：逐次逼近AD转换器和逐次逼近AD转换方法
公开(公告)号：US09013345B2
公开(公告)日：2015-04-21
申请号：US14161790
申请日：2014-01-23
申请人： Tomoki Segawa , Fumihiro Inoue
发明人： Tomoki Segawa , Fumihiro Inoue
IPC分类号： H03M1/12 , H03M1/06 , H03M1/40
CPC分类号： H03M1/1245 , H03M1/0687 , H03M1/0697 , H03M1/40
摘要： A successive approximation AD converter includes a DA converter that converts a higher conversion data greater than an approximate value into an analog higher converted voltage and converts a lower conversion data less than the approximate value into an analog lower converted voltage; a sample-and-hold circuit that samples and holds voltage differences between an input voltage and each of the higher converted voltage and the lower converted voltage; a comparator that outputs a first comparison result indicating whether the input voltage is greater or less than the higher converted voltage and a second comparison result indicating whether the input voltage is greater or less than the lower converted voltage; and an operation unit that changes the approximate value based on the first comparison result and the second comparison result, and changes a next higher conversion data and a next lower conversion data based on the changed approximate value.
摘要翻译：逐次逼近AD转换器包括DA转换器，其将大于近似值的较高转换数据转换为模拟更高转换电压，并将小于近似值的较低转换数据转换为模拟较低转换电压; 采样和保持电路，其对输入电压和较高转换电压和较低转换电压之间的电压差进行采样和保持; 输出表示所述输入电压是大于还是小于所述较高转换电压的第一比较结果的比较器，以及指示所述输入电压是否大于或小于所述较低转换电压的第二比较结果; 以及基于第一比较结果和第二比较结果改变近似值的操作单元，并且基于改变的近似值来改变下一较高转换数据和下一较低转换数据。

10. 发明授权

US08823574B2 Successive approximation type A/D converter, method of controlling successive approximation type A/D converter, solid-state imaging device, and imaging apparatus 有权
标题翻译：连续逼近型A / D转换器，控制逐次逼近型A / D转换器的方法，固态成像装置和成像装置
公开(公告)号：US08823574B2
公开(公告)日：2014-09-02
申请号：US13222062
申请日：2011-08-31
申请人： Masaki Sakakibara
发明人： Masaki Sakakibara
IPC分类号： H03M1/06 , H03M1/40 , H03M1/46
CPC分类号： H03M1/0675 , H03M1/066 , H03M1/20 , H03M1/40 , H03M1/462 , H03M1/806 , H04N5/363 , H04N5/378
摘要： A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.
摘要翻译：逐次逼近型A / D转换器包括：产生参考信号的参考信号产生部分; 比较将输入的模拟信号与参考信号进行比较并将模拟信号转换为数字信号的比较器; 以及控制部，通过对比较器的模拟信号多次执行A / D转换处理，控制参考信号进行过采样，使得模拟信号在A的第一个A处被A / D转换成N位的数字值 / D转换处理，并且使得从第（N-n）个或更低阶的较低位开始执行第二和随后的A / D转换处理，其中在第一（N-n）位获得的N位数字值的高n位 A / D转换过程固定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式