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1. 发明授权

US07973384B2 Phase change memory cell including multiple phase change material portions 有权
标题翻译：相变存储单元包括多个相变材料部分
公开(公告)号：US07973384B2
公开(公告)日：2011-07-05
申请号：US11265377
申请日：2005-11-02
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： H01L45/00
CPC分类号： H01L45/1608 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A memory cell includes a first electrode, a second electrode, and a first portion of phase-change material contacting the first electrode. The memory cell includes a second portion of phase-change material contacting the second electrode and a third portion of phase-change material between the first portion and the second portion. A phase-change material composition of the third portion and the second portion gradually transitions from the third portion to the second portion.
摘要翻译：存储单元包括第一电极，第二电极和与第一电极接触的相变材料的第一部分。存储单元包括在第一部分和第二部分之间接触第二电极的相变材料的第二部分和相变材料的第三部分。第三部分和第二部分的相变材料组合物从第三部分逐渐过渡到第二部分。

2. 发明授权

US07876606B2 Integrated circuit for programming a memory cell 有权
标题翻译：用于编程存储单元的集成电路
公开(公告)号：US07876606B2
公开(公告)日：2011-01-25
申请号：US12166755
申请日：2008-07-02
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2029/0411
摘要： An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.
摘要翻译：集成电路包括电阻变化存储单元阵列。阵列包括第一部分。集成电路包括被配置为将第一脉冲宽度的设置脉冲施加到第一部分中的第一存储器单元以设置第一存储单元的电路。第一脉冲宽度基于第一部分的预定误差百分比。

3. 发明授权

US07869257B2 Integrated circuit including diode memory cells 有权
标题翻译：集成电路包括二极管存储单元
公开(公告)号：US07869257B2
公开(公告)日：2011-01-11
申请号：US11957964
申请日：2007-12-17
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/003 , G11C11/36 , G11C13/0004 , G11C13/0023 , G11C2213/71 , G11C2213/72 , G11C2213/78 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1675 , H01L45/1683
摘要： The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell.
摘要翻译：集成电路包括晶体管和耦合到晶体管的触点。集成电路包括耦合到触点的第一二极管电阻率变化材料存储单元和耦合到触点的第二二极管电阻率变化材料存储单元。第二二极管电阻率变化材料存储单元位于第一二极管电阻率变化材料存储单元上方。

4. 发明申请

US20100321990A1 Memory Including Vertical Bipolar Select Device and Resistive Memory Element 失效
标题翻译：包括垂直双极选择器件和电阻式存储元件的存储器
公开(公告)号：US20100321990A1
公开(公告)日：2010-12-23
申请号：US12853791
申请日：2010-08-10
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： G11C11/00 , H01L21/8222
CPC分类号： H01L27/2463 , G11C13/0004 , G11C2213/79 , H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148
摘要： A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base.
摘要翻译：存储器包括包括第一基极和第一发射极的第一垂直双极选择器件，耦合到第一发射极的第一相变元件，包括第二基极和第二发射极的第二垂直双极选择器件，第二相变元件耦合并且与第一基底和第二基底接触的掩埋字线。

5. 发明申请

US20100293350A1 METHOD OF OPERATING AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT AND MEMORY MODULE 有权
标题翻译：集成电路，集成电路和存储器模块的运行方法
公开(公告)号：US20100293350A1
公开(公告)日：2010-11-18
申请号：US12687951
申请日：2010-01-15
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： G06F12/16 , G06F12/00 , G11C11/00
CPC分类号： G11C11/16 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0035 , G11C13/0069
摘要： According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistance changing memory cells grouped into physical memory units is provided. The method includes: Monitoring writing access numbers assigned to the physical memory units, each writing access number reflecting the number of writing accesses to the physical memory unit to which the writing access number is assigned; if the value of a writing access number assigned to a first physical memory unit exceeds a writing access threshold value, a data exchange process is carried out during which the data content stored within the first physical memory unit is exchanged with the data content of a second physical memory unit having a writing access number of a lower value.
摘要翻译：根据本发明的一个实施例，提供了一种操作集成电路的方法，该集成电路包括分组成物理存储器单元的多个电阻变化存储器单元。该方法包括：监视分配给物理存储器单元的写入访问号码，每个写入访问号码反映写入访问次数到写入访问号码的物理存储单元; 如果分配给第一物理存储器单元的写访问号码的值超过写访问阈值，则执行数据交换处理，在该数据交换处理期间，存储在第一物理存储单元内的数据内容与第二物理存储单元的数据内容交换物理存储单元具有较低值的写入访问号。

6. 发明授权

US07778070B2 Memory with dynamic redundancy configuration 有权
标题翻译：具有动态冗余配置的内存
公开(公告)号：US07778070B2
公开(公告)日：2010-08-17
申请号：US12120946
申请日：2008-05-15
申请人： Thomas Nirschl , Thomas Happ , Jan Boris Philipp
发明人： Thomas Nirschl , Thomas Happ , Jan Boris Philipp
IPC分类号： G11C11/00
CPC分类号： G11C29/44 , G11C11/5678 , G11C13/0007 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C29/42 , G11C29/4401 , G11C29/76 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208 , G11C2213/32
摘要： One embodiment of the invention relates to a method for repairing a memory array. In the method, a group of at least one memory cell is dynamically analyzed to determine whether the memory array includes at least one faulty cell that no longer properly stores data. If the group includes at least one faulty cell, at least the at least one faulty cell is associated with at least another cell. Other methods, devices, and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及一种用于修复存储器阵列的方法。在该方法中，动态地分析至少一个存储器单元的组，以确定存储器阵列是否包括不再适当地存储数据的至少一个故障单元。如果组包括至少一个有故障的小区，则至少一个故障小区与至少另一个小区相关联。还公开了其它方法，装置和系统。

7. 发明授权

US07759770B2 Integrated circuit including memory element with high speed low current phase change material 有权
标题翻译：集成电路包括具有高速低电流相变材料的存储元件
公开(公告)号：US07759770B2
公开(公告)日：2010-07-20
申请号：US12143948
申请日：2008-06-23
申请人： Thomas Happ , Jan Boris Philipp
发明人： Thomas Happ , Jan Boris Philipp
IPC分类号： H01L29/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/144 , H01L45/1625
摘要： An integrated circuit includes a first electrode, a second electrode, and a memory element coupled to the first electrode and to the second electrode, the memory element includes fast-operation resistance changing material doped with dielectric material.
摘要翻译：集成电路包括第一电极，第二电极和耦合到第一电极和第二电极的存储元件，存储元件包括掺杂有电介质材料的快速操作的电阻改变材料。

8. 发明授权

US07679074B2 Integrated circuit having multilayer electrode 有权
标题翻译：具有多层电极的集成电路
公开(公告)号：US07679074B2
公开(公告)日：2010-03-16
申请号：US11766822
申请日：2007-06-22
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/128 , H01L45/144 , H01L45/148 , H01L45/16 , Y02P80/30
摘要： An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a second electrode and a resistivity changing material between the first electrode and the second electrode.
摘要翻译：集成电路包括接触件和耦合到接触件的第一电极。第一电极包括至少两个电极材料层。所述至少两个电极材料层包括不同的材料。集成电路包括在第一电极和第二电极之间的第二电极和电阻率变化材料。

9. 发明申请

US20100002498A1 INTEGRATED CIRCUIT FOR PROGRAMMING A MEMORY CELL 有权
标题翻译：用于编程存储器单元的集成电路
公开(公告)号：US20100002498A1
公开(公告)日：2010-01-07
申请号：US12166755
申请日：2008-07-02
申请人： Jan Boris Philipp , Thomas Happ
发明人： Jan Boris Philipp , Thomas Happ
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0092 , G11C2029/0411
摘要： An integrated circuit includes an array of resistance changing memory cells. The array includes a first portion. The integrated circuit includes a circuit configured to apply a set pulse having a first pulse width to a first memory cell in the first portion to set the first memory cell. The first pulse width is based on a predetermined error percentage for the first portion.
摘要翻译：集成电路包括电阻变化存储单元阵列。阵列包括第一部分。集成电路包括被配置为将第一脉冲宽度的设置脉冲施加到第一部分中的第一存储器单元以设置第一存储单元的电路。第一脉冲宽度基于第一部分的预定误差百分比。

10. 发明授权

US07551476B2 Resistive memory having shunted memory cells 有权
标题翻译：具有分流存储单元的电阻存储器
公开(公告)号：US07551476B2
公开(公告)日：2009-06-23
申请号：US11541973
申请日：2006-10-02
申请人： Thomas Nirschl , Thomas Happ , Jan Boris Philipp
发明人： Thomas Nirschl , Thomas Happ , Jan Boris Philipp
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2013/0054 , G11C2211/5632 , G11C2211/5634 , G11C2213/79
摘要： A memory includes a bit line and a plurality of resistive memory cells coupled to the bit line. Each resistive memory cell is programmable to each of at least three resistance states. The memory includes a first resistor for selectively coupling to the bit line to form a first current divider with a selected memory cell during a read operation.
摘要翻译：存储器包括位线和耦合到位线的多个电阻存储器单元。每个电阻式存储器单元可编程为至少三个电阻状态中的每一个。存储器包括用于选择性地耦合到位线以在读取操作期间与选择的存储器单元形成第一分流器的第一电阻器。

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