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1. 发明授权

US08274106B2 DRAM layout with vertical FETs and method of formation 有权
标题翻译：具有垂直FET的DRAM布局和形成方法
公开(公告)号：US08274106B2
公开(公告)日：2012-09-25
申请号：US13170050
申请日：2011-06-27
申请人： Todd R. Abbott , H. Montgomery Manning
发明人： Todd R. Abbott , H. Montgomery Manning
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10808 , H01L27/10876 , Y10S257/908
摘要： DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
摘要翻译：具有约4F2的单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。掩埋位线包括硅化物材料并且被设置在衬底的表面下方。字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。至少一个掩埋位线与垂直晶体管的至少一个垂直栅电极正交。

2. 发明授权

US07262089B2 Methods of forming semiconductor structures 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07262089B2
公开(公告)日：2007-08-28
申请号：US10800196
申请日：2004-03-11
申请人： Todd R. Abbott , H. Montgomery Manning
发明人： Todd R. Abbott , H. Montgomery Manning
IPC分类号： H01L21/8424 , H01L21/20 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10885 , H01L27/10841 , H01L27/10888 , H01L27/10891
摘要： The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.
摘要翻译：本发明包括具有掩埋的含硅化物的位线的半导体结构。可以在位线上形成垂直的环绕栅极晶体管结构。环绕栅极晶体管结构可以结合到诸如DRAM器件的存储器件中。本发明可用于形成4F 2 DRAM器件。

3. 发明授权

US07453103B2 Semiconductor constructions 失效
标题翻译：半导体结构
公开(公告)号：US07453103B2
公开(公告)日：2008-11-18
申请号：US11285424
申请日：2005-11-22
申请人： Todd R. Abbott , H. Montgomery Manning
发明人： Todd R. Abbott , H. Montgomery Manning
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L27/10885 , H01L27/10841 , H01L27/10888 , H01L27/10891
摘要： The invention includes semiconductor structures having buried silicide-containing bitlines. Vertical surround gate transistor structures can be formed over the bitlines. The surround gate transistor structures can be incorporated into memory devices, such as, for example, DRAM devices. The invention can be utilized for forming 4F2 DRAM devices.
摘要翻译：本发明包括具有掩埋的含硅化物的位线的半导体结构。可以在位线上形成垂直的环绕栅极晶体管结构。环绕栅极晶体管结构可以结合到诸如DRAM器件的存储器件中。本发明可用于形成4F 2 DRAM器件。

4. 发明授权

US07768051B2 DRAM including a vertical surround gate transistor 有权
标题翻译： DRAM包括垂直环绕栅极晶体管
公开(公告)号：US07768051B2
公开(公告)日：2010-08-03
申请号：US11188507
申请日：2005-07-25
申请人： Todd R. Abbott
发明人： Todd R. Abbott
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10888 , H01L27/10891
摘要： DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.
摘要翻译：具有小于约4F2的特征尺寸的DRAM存储单元包括垂直环绕栅晶体管，其被配置为减小对缩小尺寸存储单元的任何短沟道效应。此外，存储单元可以有利地包括减少的电阻字线触点和减小的电阻位线触点，这可能由于字线和位线触点的降低的电阻而增加存储器件的速度。

5. 发明授权

US07560336B2 DRAM layout with vertical FETs and method of formation 有权
标题翻译：具有垂直FET的DRAM布局和形成方法
公开(公告)号：US07560336B2
公开(公告)日：2009-07-14
申请号：US11328150
申请日：2006-01-10
申请人： Todd R. Abbott
发明人： Todd R. Abbott
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/0214 , H01L27/10852 , H01L27/10876
摘要： DRAM cell arrays having a cell area of less than about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
摘要翻译：具有小于约4F2的单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。掩埋位线包括硅化物材料并且被设置在衬底的表面下方。字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。掩埋位线中的至少一个与垂直晶体管的至少一个垂直栅电极不正交。

6. 发明授权

US07365385B2 DRAM layout with vertical FETs and method of formation 有权
标题翻译：具有垂直FET的DRAM布局和形成方法
公开(公告)号：US07365385B2
公开(公告)日：2008-04-29
申请号：US10928315
申请日：2004-08-30
申请人： Todd R. Abbott
发明人： Todd R. Abbott
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/0214 , H01L27/10852 , H01L27/10876
摘要： DRAM cell arrays having a cell area of less than about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
摘要翻译：具有小于约4F 2的单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。掩埋位线包括硅化物材料并且被设置在衬底的表面下方。字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。掩埋位线中的至少一个与垂直晶体管的至少一个垂直栅电极不正交。

7. 发明授权

US06812529B2 Suppression of cross diffusion and gate depletion 有权
公开(公告)号：US06812529B2
公开(公告)日：2004-11-02
申请号：US09808864
申请日：2001-03-15
申请人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
发明人： John D. Trivedi , Zhongze Wang , Chih-Chen Cho , Mike Violette , Todd R. Abbott
IPC分类号： H01L2949
CPC分类号： G11C11/412 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L27/11 , H01L27/1104
摘要： According to the present invention, an ultrathin buried diffusion barrier layer (UBDBL) is formed over all or part of the doped polysilicon layer of a polysilicide structure composed of the polycrystalline silicon film and an overlying film of a metal, metal silicide, or metal nitride. More specifically, according to one embodiment of the present invention, a memory cell is provided comprising a semiconductor substrate, a P well, an N well, an N type active region, a P type active region, an isolation region, a polysilicide gate electrode structure, and a diffusion barrier layer. The P well is formed in the semiconductor substrate. The N well is formed in the semiconductor substrate adjacent to the P well. The N type active region is defined in the P well and the P type active region is defined in the N well. The isolation region is arranged to isolate the N type active region from the P type active region. The polysilicide gate electrode structure is composed of a polycrystalline silicon film and an overlying metal, metal silicide, or metal nitride film. The polycrystalline silicon film comprises an N+ polysilicon layer formed with the N type active region and a P+ polysilicon layer formed with the P type active region. The diffusion barrier layer is formed in the polysilicide gate electrode structure over a substantial portion of the polycrystalline silicon film between the polycrystalline silicon film and the metal, metal silicide, or metal nitride film.

8. 发明授权

US06806134B2 Sidewall strap for complementary semiconductor structures and method of making same 失效
标题翻译：互补半导体结构的侧壁带及其制造方法
公开(公告)号：US06806134B2
公开(公告)日：2004-10-19
申请号：US10205131
申请日：2002-07-24
申请人： Jigish D. Trivedi , Todd R. Abbott , Zhongze Wang
发明人： Jigish D. Trivedi , Todd R. Abbott , Zhongze Wang
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L21/823864 , H01L21/823871
摘要： Devices, structures, and methods for enhancing devices using dual-doped polycrystalline silicon are discussed. One aspect of the present invention includes a p-type strip having a top, a bottom, two sides, and two ends; an n-type strip having a top, a bottom, two sides, and two ends; and a conductive inhibitor strip that adjoins a portion of one of the two sides of the p-type strip and a portion of one of the two sides of the n-type strip so as to inhibit cross-diffusion between the p-type strip and the n-type strip while electrical connection between n-type and p-type polycrystalline silicon is maintained.
摘要翻译：讨论了使用双掺杂多晶硅增强器件的器件，结构和方法。本发明的一个方面包括具有顶部，底部，两侧和两端的p型条带; 具有顶部，底部，两侧和两端的n型条带; 以及导电抑制带，其邻接p型条的两侧中的一方的一部分和n型条的两侧的一部分中的一部分，以便抑制p型条和同时保持n型和p型多晶硅之间的电连接。

9. 发明授权

US06727168B2 Method of forming local interconnects 有权
标题翻译：形成局部互连的方法
公开(公告)号：US06727168B2
公开(公告)日：2004-04-27
申请号：US10001758
申请日：2001-10-24
申请人： Todd R. Abbott
发明人： Todd R. Abbott
IPC分类号： H01L214763
CPC分类号： H01L21/823481 , H01L21/76895 , H01L21/823475
摘要： A first dielectric layer is formed over a first transistor gate and a second transistor source/drain region. Contact openings are formed in the first dielectric layer to the first transistor gate and to the second transistor source/drain region. A second dielectric layer is formed over the first dielectric layer and to within the contact openings. The second dielectric layer is etched selectively relative to the first dielectric layer to form at least a portion of a local interconnect outline within the second dielectric layer to extend between the first transistor gate and the second transistor source/drain region. The etching removes at least some of the second dielectric layer within the contact openings. Conductive material is formed within the local interconnect outline within the second dielectric layer which electrically connects the first transistor gate with the second transistor source/drain region. Other aspects are disclosed.
摘要翻译：在第一晶体管栅极和第二晶体管源极/漏极区域上形成第一介电层。在第一电介质层中形成接触开口到第一晶体管栅极和第二晶体管源极/漏极区域。第二电介质层形成在第一电介质层上并且在接触开口内。相对于第一介电层选择性地蚀刻第二电介质层，以形成第二电介质层内的局部互连轮廓的至少一部分，以在第一晶体管栅极和第二晶体管源极/漏极区域之间延伸。蚀刻去除接触开口内的第二介电层的至少一些。导电材料形成在将第一晶体管栅极与第二晶体管源极/漏极区域电连接的第二介电层内的局部互连轮廓内。公开其他方面。

10. 发明授权

US06677650B2 Silicon plugs and local interconnect for embedded memory and system-on-chip (SOC) applications 有权
标题翻译：硅插头和本地互连，用于嵌入式存储器和片上系统（SOC）应用
公开(公告)号：US06677650B2
公开(公告)日：2004-01-13
申请号：US10047349
申请日：2002-01-14
申请人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
发明人： Mark Fischer , Jigish D. Trivedi , Charles H. Dennison , Todd R. Abbott , Raymond A. Turi
IPC分类号： H01L23532
CPC分类号： H01L27/10894 , G11C2207/104 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L27/10855 , H01L27/10888
摘要： A process for fabricating system-on-chip devices which contain embedded DRAM along with other components such as SRAM or logic circuits is disclosed. Local interconnects, via salicides and tungsten are formed subsequent to polysilicon plugs required for the operation of the DRAM and SRAM or logic. Also disclosed are systems-on-chips MIM/MIS capacitive devices produced by the inventive process.
摘要翻译：公开了一种用于制造片上系统的方法，其中包含嵌入式DRAM以及诸如SRAM或逻辑电路的其它组件。在DRAM和SRAM或逻辑的操作所需的多晶硅插塞之后形成通过硫化物和钨的局部互连。还公开了由本发明方法制造的片上系统MIM / MIS电容性器件。

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