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1. 发明授权

US08782381B2 Dynamically rewriting branch instructions in response to cache line eviction 有权
标题翻译：动态地重写分支指令以响应缓存线驱逐
公开(公告)号：US08782381B2
公开(公告)日：2014-07-15
申请号：US13444890
申请日：2012-04-12
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F8/4442 , G06F9/3806 , G06F12/0875 , G06F12/12
摘要： Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs.
摘要翻译：提供用于从数据处理系统的指令高速缓存中驱逐高速缓存行的机制。机制存储当前高速缓存行中代码的一部分，直接或间接地定位当前高速缓存行中代码部分的调用站点的链接列表。确定当前高速缓存行是否将从指令高速缓存中逐出。处理呼叫站点的链接列表以识别具有相关联的分支存根的一个或多个重写的分支指令，其直接或间接地对目标当前高速缓存行中的代码部分。此外，重写一个或多个重写的分支指令，以基于相关联的分支存根中的信息将一个或多个重写的分支指令恢复到原始状态。

2. 发明授权

US08627051B2 Dynamically rewriting branch instructions to directly target an instruction cache location 有权
标题翻译：动态地重写分支指令直接指向指令高速缓存位置
公开(公告)号：US08627051B2
公开(公告)日：2014-01-07
申请号：US13442919
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.
摘要翻译：提供了用于在代码的一部分中动态地重写分支指令的机制。这些机制在代码的一部分中执行分支指令。这些机制确定分支指令的目标指令是否存在于与处理器相关联的指令高速缓存中。此外，响应于确定目标指令存在于指令高速缓存中，机制直接将代码部分的执行分支到指令高速缓存中的目标指令，而不需要来自指令高速缓存运行时系统的干预。此外，响应于确定目标指令不能被确定为存在于指令高速缓存中，这些机制将代码部分的执行重定向到指令高速缓存运行时系统。

3. 发明授权

US08713548B2 Rewriting branch instructions using branch stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US08713548B2
公开(公告)日：2014-04-29
申请号：US13443188
申请日：2012-04-10
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

4. 发明授权

US08631225B2 Dynamically rewriting branch instructions to directly target an instruction cache location 有权
公开(公告)号：US08631225B2
公开(公告)日：2014-01-14
申请号：US12823194
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/44
CPC分类号： G06F9/3806 , G06F12/0875
摘要： Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache.

5. 发明授权

US09600253B2 Arranging binary code based on call graph partitioning 有权
公开(公告)号：US09600253B2
公开(公告)日：2017-03-21
申请号：US13444907
申请日：2012-04-12
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.

6. 发明授权

US09459851B2 Arranging binary code based on call graph partitioning 有权
标题翻译：基于调用图分区来排列二进制代码
公开(公告)号：US09459851B2
公开(公告)日：2016-10-04
申请号：US12823244
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4442
摘要： Mechanisms are provided for arranging binary code to reduce instruction cache conflict misses. These mechanisms generate a call graph of a portion of code. Nodes and edges in the call graph are weighted to generate a weighted call graph. The weighted call graph is then partitioned according to the weights, affinities between nodes of the call graph, and the size of cache lines in an instruction cache of the data processing system, so that binary code associated with one or more subsets of nodes in the call graph are combined into individual cache lines based on the partitioning. The binary code corresponding to the partitioned call graph is then output for execution in a computing device.
摘要翻译：提供了用于布置二进制代码以减少指令高速缓存冲突未命中的机制。这些机制产生一部分代码的调用图。调用图中的节点和边被加权以生成加权调用图。然后根据权重，调用图的节点之间的亲和度和数据处理系统的指令高速缓存中的高速缓存行的大小来分配加权调用图，使得与一个或多个节点的子集相关联的二进制代码调用图被组合到基于分区的各个高速缓存行。然后输出与划分的调用图对应的二进制代码，以在计算设备中执行。

7. 发明授权

US08522225B2 Rewriting branch instructions using branch stubs 有权
标题翻译：使用分支存根重写分支指令
公开(公告)号：US08522225B2
公开(公告)日：2013-08-27
申请号：US12823204
申请日：2010-06-25
申请人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
发明人： Tong Chen , Brian Flachs , Brad W. Michael , Mark R. Nutter , John K. P. O'Brien , Kathryn M. O'Brien , Tao Zhang
IPC分类号： G06F9/45
CPC分类号： G06F8/4436 , G06F8/433 , G06F8/4442
摘要： Mechanisms are provided for rewriting branch instructions in a portion of code. The mechanisms receive a portion of source code having an original branch instruction. The mechanisms generate a branch stub for the original branch instruction. The branch stub stores information about the original branch instruction including an original target address of the original branch instruction. Moreover, the mechanisms rewrite the original branch instruction so that a target of the rewritten branch instruction references the branch stub. In addition, the mechanisms output compiled code including the rewritten branch instruction and the branch stub for execution by a computing device. The branch stub is utilized by the computing device at runtime to determine if execution of the rewritten branch instruction can be redirected directly to a target instruction corresponding to the original target address in an instruction cache of the computing device without intervention by an instruction cache runtime system.
摘要翻译：提供了用于在一部分代码中重写分支指令的机制。该机制接收一部分具有原始分支指令的源代码。机制为原始分支指令生成分支存根。分支存根存储关于原始分支指令的信息，包括原始分支指令的原始目标地址。此外，机制重写原始分支指令，使得重写的分支指令的目标引用分支存根。此外，机制输出编译代码，包括重写的分支指令和分支存根，以供计算设备执行。计算设备在运行时利用分支存根来确定重写的分支指令的执行是否可以被直接重定向到与计算设备的指令高速缓存中的原始目标地址相对应的目标指令，而无需指令高速缓存运行时系统的干预。

8. 发明授权

US08468539B2 Tracking and detecting thread dependencies using speculative versioning cache 有权
标题翻译：使用推测版本缓存来跟踪和检测线程依赖关系
公开(公告)号：US08468539B2
公开(公告)日：2013-06-18
申请号：US12553314
申请日：2009-09-03
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Lakshminarayanan Renganarayana , Xiaotong Zhuang
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Lakshminarayanan Renganarayana , Xiaotong Zhuang
IPC分类号： G06F9/46
CPC分类号： G06F9/3814 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3859
摘要： Mechanisms are provided for tracking dependencies of threads in a multi-threaded computer program execution. The mechanisms detect a dependency of a first thread's execution on results of a second thread's execution in an execution flow of the multi-threaded computer program. The mechanisms further store, in a hardware thread dependency vector storage associated with the first thread's execution, an identifier of the dependency by setting at least one bit in the hardware thread dependency vector storage corresponding to the second thread. Moreover, the mechanisms schedule tasks performed by the multi-threaded computer program based on the hardware thread dependency vector storage to minimize squashing of threads.
摘要翻译：提供了用于跟踪多线程计算机程序执行中线程依赖性的机制。该机制检测第一个线程执行对多线程计算机程序执行流程中第二个线程执行结果的依赖性。这些机制通过在与第二线程相对应的硬件线程相关性向量存储中设置至少一个比特来进一步存储与第一线程的执行相关联的硬件线程依赖向量存储中的依赖关系的标识符。此外，该机制基于硬件线程依赖向量存储来调度由多线程计算机程序执行的任务以最小化线程的挤压。

9. 发明授权

US08087011B2 Domain stretching for an advanced dual-representation polyhedral loop transformation framework 失效
标题翻译：领域拉伸为先进的双重表示多面体环转换框架
公开(公告)号：US08087011B2
公开(公告)日：2011-12-27
申请号：US11861503
申请日：2007-09-26
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/452
摘要： Mechanisms for domain stretching for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for stretching the domains of statements in a program loop view of the source code to thereby normalize the domains.
摘要翻译：提供了用于高级双重表示多面体环转换框架的域拉伸的机制。说明性实施例的机制通过提供用于在通过源代码的多面体环转换优化生成的中间表示中对各个语句实例执行代码生成变换的机制来解决已知的基于多面体循环变换的方法的弱点。这些代码生成转换具有重要的属性，它们不改变中间表示中的语句的程序顺序。该属性允许通过示例性实施例的新的重新导入路径将代码生成转换的结果提供给程序语句视图中的多面体循环变换机制，用于附加优化。另外，提供了用于在源代码的程序循环视图中拉伸语句的域的机制，从而使域标准化。

10. 发明授权

US08056065B2 Stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework 失效
标题翻译：在存在高级双重表示多面体循环转换框架的条件下的稳定转换
公开(公告)号：US08056065B2
公开(公告)日：2011-11-08
申请号：US11861512
申请日：2007-09-26
申请人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
发明人： Alexandre E. Eichenberger , John K. P. O'Brien , Kathryn M. O'Brien , Nicolas T. Vasilache
IPC分类号： G06F9/45
CPC分类号： G06F8/447
摘要： Mechanisms for stable transitions in the presence of conditionals for an advanced dual-representation polyhedral loop transformation framework are provided. The mechanisms of the illustrative embodiments address the weaknesses of the known polyhedral loop transformation based approaches by providing mechanisms for performing code generation transformations on individual statement instances in an intermediate representation generated by the polyhedral loop transformation optimization of the source code. These code generation transformations have the important property that they do not change program order of the statements in the intermediate representation. This property allows the result of the code generation transformations to be provided back to the polyhedral loop transformation mechanisms in a program statement view, via a new re-entrance path of the illustrative embodiments, for additional optimization. In addition, mechanisms are provided for ensuring code stabilization in the presence of conditions such that code bloat is not encountered during re-entrance.
摘要翻译：提供了在高级双重表示多面体环转换框架的条件下存在稳定转换的机制。说明性实施例的机制通过提供用于在通过源代码的多面体环转换优化生成的中间表示中对各个语句实例执行代码生成变换的机制来解决已知的基于多面体循环变换的方法的弱点。这些代码生成转换具有重要的属性，它们不改变中间表示中的语句的程序顺序。该属性允许通过示例性实施例的新的重新导入路径将代码生成转换的结果提供给程序语句视图中的多面体循环变换机制，用于附加优化。此外，还提供了在存在条件的情况下确保代码稳定的机制，使得在重入期间不会遇到代码膨胀。

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