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1. 发明申请

US20080185652A1 Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors 有权
标题翻译：通过串联电阻同时调节多个存储单元
公开(公告)号：US20080185652A1
公开(公告)日：2008-08-07
申请号：US12060922
申请日：2008-04-02
申请人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Chung H. Lam , Gerhard I. Meijer
发明人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Chung H. Lam , Gerhard I. Meijer
IPC分类号： H01L23/62 , H01L21/8234
CPC分类号： H01L27/0629 , H01L27/101 , H01L27/24
摘要： Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.
摘要翻译：公开了一种半导体结构和方法，其允许在具有多个存储器单元的非易失性存储器件中同时对多个存储器元件进行电压/电流调节。该结构和方法结合使用与存储器元件串联连接的电阻器来限制电流通过存储器元件。具体地，该方法和结构在存储器单元上方的晶片表面上和/或存储器单元内的永久串联电阻器上并入一个橡皮布暂时串联电阻器。在调节过程中，一旦调节了这些电阻，这些电阻就可以保护各个存储元件中的过渡金属氧化物免受损坏（即烧坏）。

2. 发明授权

US07541608B2 Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells 失效
标题翻译：存储器件以及通过同时调节多个存储单元中的过渡金属氧化物层来制造器件的方法
公开(公告)号：US07541608B2
公开(公告)日：2009-06-02
申请号：US12030927
申请日：2008-02-14
申请人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Chung H. Lam , Gerhard I. Meijer
发明人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Chung H. Lam , Gerhard I. Meijer
IPC分类号： H01L47/00
CPC分类号： H01L27/101 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , Y10S438/90
摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
摘要翻译：公开了包含一系列单个或双重存储器单元的非易失性存储器件。单个存储器单元基本上是“U”形的。双重存储单元包括两个基本上“U”形的存储单元。每个存储单元包括具有夹在两个导电层之间的双稳态层的存储元件。临时导体可以应用于一系列的电池并且用于批量地调节电池的双稳态层。此外，由于电池的“U”形状，可以使用交叉点线阵列来连接一系列电池。交叉点线阵列允许每个单元的存储元件被单独识别和寻址用于存储信息，并且还允许使用块擦除处理同时擦除存储在串联中的所有单元中的存储器元件中的信息。

3. 发明申请

US20080131995A1 MEMORY DEVICE AND MEHTOD OF MANUFACTURING THE DEVICE BY SIMULATANEOUSLY CONDITIONING TRANSITION METAL OXIDE LAYERS IN A PLURALITY OF MEMORY CELLS 失效
标题翻译：通过在大量存储器电池中模拟过渡金属氧化物层来制造器件的存储器件和器件
公开(公告)号：US20080131995A1
公开(公告)日：2008-06-05
申请号：US12030927
申请日：2008-02-14
申请人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Chung H. Lam , Gerhard I. Meijer
发明人： Toshijaru Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Chung H. Lam , Gerhard I. Meijer
IPC分类号： H01L21/00
CPC分类号： H01L27/101 , H01L27/115 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , Y10S438/90
摘要： Disclosed are non-volatile memory devices that incorporate a series of single or double memory cells. The single memory cells are essentially “U” shaped. The double memory cells comprise two essentially “U” shaped memory cells. Each memory cell comprises a memory element having a bi-stable layer sandwiched between two conductive layers. A temporary conductor may be applied to a series of cells and used to bulk condition the bi-stable layers of the cells. Also, due to the “U” shape of the cells, a cross point wire array may be used to connect a series of cells. The cross point wire array allows the memory elements of each cell to be individually identified and addressed for storing information and also allows for the information stored in the memory elements in all of the cells in the series to be simultaneously erased using a block erase process.
摘要翻译：公开了包含一系列单个或双重存储器单元的非易失性存储器件。单个存储器单元基本上是“U”形的。双重存储单元包括两个基本上“U”形的存储单元。每个存储单元包括具有夹在两个导电层之间的双稳态层的存储元件。临时导体可以应用于一系列的电池并且用于批量地调节电池的双稳态层。此外，由于电池的“U”形状，可以使用交叉点线阵列来连接一系列电池。交叉点线阵列允许每个单元的存储元件被单独识别和寻址用于存储信息，并且还允许使用块擦除处理同时擦除存储在串联中的所有单元中的存储器元件中的信息。

4. 发明申请

US20080128811A1 SEMICONDUCTOR DEVICES WITH BURIED ISOLATION REGIONS 审中-公开
标题翻译：带有分离隔离区的半导体器件
公开(公告)号：US20080128811A1
公开(公告)日：2008-06-05
申请号：US12018886
申请日：2008-01-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
IPC分类号： H01L29/786
CPC分类号： H01L29/0653 , B82Y10/00 , H01L21/28114 , H01L21/3086 , H01L21/31144 , H01L21/76224 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L29/0649 , H01L29/0657 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66575 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654 , H01L29/78684
摘要： Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.
摘要翻译：半导体结构和形成半导体结构的方法。包括纳米结构或使用纳米结构制造的半导体结构。形成半导体结构的方法包括使用纳米掩模生成纳米结构，并使用所生成的纳米结构进行附加的半导体加工步骤。

5. 发明申请

US20070290394A1 METHOD AND STRUCTURE FOR FORMING SELF-PLANARIZING WIRING LAYERS IN MULTILEVEL ELECTRONIC DEVICES 审中-公开
标题翻译：在多个电子设备中形成自平坦布线的方法和结构
公开(公告)号：US20070290394A1
公开(公告)日：2007-12-20
申请号：US11425210
申请日：2006-06-20
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
IPC分类号： B28B1/48
CPC分类号： H01L21/02164 , H01L21/0228 , H01L21/31608 , H01L21/32051 , H01L21/76801 , H01L21/76838 , H01L21/7684 , H01L23/53276 , H01L2924/0002 , Y10T428/249924 , H01L2924/00
摘要： A method for forming a self-planarizing wiring layer for a semiconductor device includes forming a mat of filament material over a semiconductor substrate, and infusing the mat with a conductive material formed at a thickness substantially corresponding to the thickness of the mat of filament material. The mat is then patterned so as to expose regions where conductive wiring is not to be present, and the infused conductive material is removed from the exposed regions. The exposed regions of the mat are infused with an insulating material, formed at a thickness substantially corresponding to the thickness of the mat of filament material.
摘要翻译：用于形成半导体器件的自平面化布线层的方法包括在半导体衬底上形成丝状材料垫，并且以基本上对应于长丝材料垫的厚度的厚度形成的导电材料注入垫。然后将垫图案化以暴露不存在导电布线的区域，并且从暴露区域去除输入的导电材料。衬垫的暴露区域注入绝缘材料，绝缘材料以基本上对应于长丝材料垫的厚度的厚度形成。

6. 发明申请

US20080217730A1 METHODS OF FORMING GAS DIELECTRIC AND RELATED STRUCTURE 审中-公开
标题翻译：形成气体电介质的方法及相关结构
公开(公告)号：US20080217730A1
公开(公告)日：2008-09-11
申请号：US11682928
申请日：2007-03-07
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/76832 , H01L21/76834
摘要： Methods of forming a gas dielectric and a related structure are disclosed. In one embodiment, the method includes providing a wiring level including at least one conductive portion within a sacrificial dielectric; forming a nanofiber layer over the wiring level; vaporizing the sacrificial dielectric by heating; evacuating the vaporized sacrificial layer; and sealing pores in the nanofiber layer.
摘要翻译：公开了形成气体电介质和相关结构的方法。在一个实施例中，该方法包括提供包括牺牲电介质内的至少一个导电部分的布线层; 在布线层上形成纳米纤维层; 通过加热蒸发牺牲电介质; 抽空蒸发的牺牲层; 并密封纳米纤维层中的孔。

7. 发明申请

US20070296937A1 ILLUMINATION LIGHT IN IMMERSION LITHOGRAPHY STEPPER FOR PARTICLE OR BUBBLE DETECTION 审中-公开
标题翻译：用于颗粒或泡沫检测的浸没式平台步进器中的照明灯
公开(公告)号：US20070296937A1
公开(公告)日：2007-12-27
申请号：US11426458
申请日：2006-06-26
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger , Peter H. Mitchell
IPC分类号： G03B27/42
CPC分类号： G03B27/42 , G03F7/70341 , G03F7/7085 , G03F7/70916
摘要： Embodiments of the invention present a system, method, etc. for illumination light in an immersion lithography stepper for particle or bubble detection. More specifically, embodiments herein provide an immersion lithography expose system comprising a wafer holder for holding a wafer, an immersion liquid for covering the wafer, an immersion head to dispense and contain said immersion liquid, and a light source adapted to lithographically expose a resist on the wafer. The system also comprises a light detector at a first location of the immersion head and a laser source at a second location within said immersion head.
摘要翻译：本发明的实施例在用于颗粒或气泡检测的浸没式光刻步进机中提供照明光的系统，方法等。更具体地，本文的实施例提供了浸没式光刻曝光系统，其包括用于保持晶片的晶片保持器，用于覆盖晶片的浸没液体，用于分配和容纳所述浸没液体的浸没头，以及适于光刻曝光抗蚀剂的光源晶圆。该系统还包括在浸没头的第一位置处的光检测器和位于所述浸没头内的第二位置处的激光源。

8. 发明授权

US07510939B2 Microelectronic structure by selective deposition 有权
标题翻译：微电子结构通过选择性沉积
公开(公告)号：US07510939B2
公开(公告)日：2009-03-31
申请号：US11307294
申请日：2006-01-31
申请人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger
发明人： Toshiharu Furukawa , Steven J. Holmes , David V. Horak , Charles W. Koburger
IPC分类号： H01L21/02 , H01L21/336
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795 , H01L29/78645
摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.
摘要翻译： finFET结构包括位于衬底上的半导体鳍片。栅电极穿过半导体鳍片。栅电极具有邻接其侧壁的间隔层。间隔层不完全覆盖半导体鳍片的侧壁。栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是衬底的相邻表面上，使得间隔层不完全覆盖半导体鳍片可以使用侧向生长方法制造其它微电子结构。

9. 发明授权

US08637400B2 Interconnect structures and methods for back end of the line integration 失效
标题翻译：用于线路集成后端的互连结构和方法
公开(公告)号：US08637400B2
公开(公告)日：2014-01-28
申请号：US13164940
申请日：2011-06-21
申请人： David V. Horak , Charles W. Koburger , Shom Ponoth , Chih-Chao Yang
发明人： David V. Horak , Charles W. Koburger , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/31 , H01L23/52
CPC分类号： G06F17/5077 , H01L21/76834 , H01L21/76885
摘要： A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.
摘要翻译：形成半导体结构的方法包括形成牺牲导电材料层。该方法还包括在牺牲导电材料层中形成沟槽。该方法还包括在沟槽中形成导电特征。该方法还包括去除对导电特征有选择性的牺牲导电材料层。该方法还包括在导电特征周围形成绝缘层以将导电特征嵌入绝缘层中。

10. 发明申请

US20080188080A1 MANDREL/TRIM ALIGNMENT IN SIT PROCESSING 有权
标题翻译：处理中的MANDREL / TRIM对齐
公开(公告)号：US20080188080A1
公开(公告)日：2008-08-07
申请号：US12062618
申请日：2008-04-04
申请人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger , Qiqing C. Quyang
发明人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger , Qiqing C. Quyang
IPC分类号： H01L21/311 , H01L21/467
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed herein is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：本文公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，需要修剪蒙版对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

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