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1. 发明授权

US09479009B2 Power system for actively maintaining operation 有权
标题翻译：电力系统积极维护运行
公开(公告)号：US09479009B2
公开(公告)日：2016-10-25
申请号：US13234625
申请日：2011-09-16
申请人： Tzung-Han Lee , Tsung-Te Lee
发明人： Tzung-Han Lee , Tsung-Te Lee
IPC分类号： H02J4/00 , H02J9/06
CPC分类号： H02J9/06 , Y10T307/305 , Y10T307/50
摘要： A power system for actively maintaining operation includes a power supply unit electrically connected to a commercial power source, a back panel electrically connected to the power supply unit and an ON/OFF control unit. The power supply unit has an OFF state and an operating state to convert the power provided by the commercial power source for outputting. The back panel converges the output of the power supply unit and provides a driving power. The ON/OFF control unit has an input detection terminal electrically connected to the commercial power source to detect whether the commercial power source supplies power and at least one operation signal terminal to output an operation signal upon judging that the commercial power source supplies power to drive the power supply unit to enter the operating state.
摘要翻译：用于主动维护操作的电力系统包括电连接到商用电源的电源单元，电连接到电源单元的后面板和ON / OFF控制单元。电源单元具有OFF状态和用于转换由商用电源提供的电力进行输出的操作状态。后面板会收敛电源单元的输出并提供驱动电源。 ON / OFF控制单元具有电连接到商用电源的输入检测端子，用于检测商用电源是否提供电力，以及至少一个操作信号端子，以在判断商用电源供电以驱动时输出操作信号电源单元进入运行状态。

2. 发明申请

US20130140620A1 Flash Memory and Manufacturing Method Thereof 审中-公开
标题翻译：闪存及其制造方法
公开(公告)号：US20130140620A1
公开(公告)日：2013-06-06
申请号：US13398853
申请日：2012-02-17
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu , Dah-Wei Liu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/11524
摘要： The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same.
摘要翻译：本发明公开了一种闪速存储器。闪速存储器包括依次设置在基板上的基板和存储器串，多个着陆焊盘，多个公共源极线，多个位线触点和至少一个位线。该存储器串包括多个存储晶体管。着陆焊盘设置在每个存储晶体管之间。公共源线和位线接触件可替换地电连接到着陆焊盘。公共线设置在公共线路触点上并与其电连接。本发明还提供制造该方法的制造方法。

3. 发明授权

US08455363B2 Method for adjusting trench depth of substrate 有权
标题翻译：调整衬底沟槽深度的方法
公开(公告)号：US08455363B2
公开(公告)日：2013-06-04
申请号：US13282593
申请日：2011-10-27
申请人： Tzung-Han Lee , Chung-Lin Huang
发明人： Tzung-Han Lee , Chung-Lin Huang
IPC分类号： H01L21/311
CPC分类号： H01L21/3065 , H01L21/3081 , H01L21/3083
摘要： A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.
摘要翻译：用于调整衬底的沟槽深度的方法具有以下步骤。在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。较窄的缓冲层的厚度比较宽的缓冲层薄。实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

4. 发明授权

US08298892B1 Fabricating method of insulator 有权
标题翻译：绝缘子的制造方法
公开(公告)号：US08298892B1
公开(公告)日：2012-10-30
申请号：US13241295
申请日：2011-09-23
申请人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
发明人： Tzung-Han Lee , Chung-Lin Huang , Ron Fu Chu
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L21/76224 , H01L29/4236
摘要： A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.
摘要翻译：一种绝缘体的制造方法，用于通过绝缘体代替衬底中的栅极结构。制造方法包括提供包括第一掩埋栅极结构的衬底的步骤。第一掩埋结构包括嵌入衬底中的第一沟槽和填充在第一沟槽中的第一栅极。第一个沟槽有第一个深度。然后，去除第一掩埋结构的第一栅极。之后，蚀刻第一沟槽下面的衬底，以将第一沟槽的深度从第一深度延伸到第三深度。最后，绝缘材料填充具有第三深度的第一沟槽以形成本发明的绝缘体。

5. 发明申请

US20120168857A1 Memory structure having a floating body and method for fabricating the same 有权
公开(公告)号：US20120168857A1
公开(公告)日：2012-07-05
申请号：US13102039
申请日：2011-05-05
申请人： Tzung-Han Lee , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7841 , H01L27/10802 , H01L29/66666 , H01L29/7827
摘要： A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.

6. 发明申请

US20120012907A1 Memory layout structure and memory structure 有权
标题翻译：内存布局结构和内存结构
公开(公告)号：US20120012907A1
公开(公告)日：2012-01-19
申请号：US12874232
申请日：2010-09-02
申请人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
发明人： Tzung-Han Lee , Chung-Lin Huang , Hsien-Wen Liu
IPC分类号： H01L27/108
CPC分类号： H01L29/4983 , H01L27/0207 , H01L27/10855 , H01L27/10876 , H01L27/10882 , H01L29/4236
摘要： A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.
摘要翻译：公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸（边缘壁），以执行侧壁接触。自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

7. 发明授权

US07586152B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US07586152B2
公开(公告)日：2009-09-08
申请号：US11949047
申请日：2007-12-03
申请人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
发明人： Tzung-Han Lee , Chih-Hao Cheng , Chung-Yuan Lee
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10891 , H01L27/10876
摘要： The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.
摘要翻译：本发明公开了一种掩埋字线的结构，其包括具有U形沟槽的半导体衬底，U形沟槽中的U形栅极介电层，U形栅极介电层上的多晶硅层，多晶硅层上的导电层和导电层上的覆盖电介质层。半导体结构可以具有最小化的尺寸，并且当由此形成凹槽时，相应地提高了积分，而不会受到短沟道效应的影响。

8. 发明授权

US07557012B2 Method for forming surface strap 有权
标题翻译：形成表带的方法
公开(公告)号：US07557012B2
公开(公告)日：2009-07-07
申请号：US11940308
申请日：2007-11-14
申请人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
发明人： Chih-Hao Cheng , Tzung-Han Lee , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10867
摘要： A method for forming a surface strap includes forming a deep trench capacitor having a conductive connection layer on its surface in the substrate and the conductive connection layer in contact with the conductive layer; forming a poly-Si layer covering the pad layer and the conductive connection layer; performing a selective ion implantation with an angle to make part of the poly-Si layer an undoped poly-Si layer; removing the undoped poly-Si layer to expose part of the conductive connection layer; etching the exposed conductive connection layer to form a recess; removing the poly-Si layer to make the exposed conductive connection layer a conductive connection strap; filling the recess with an insulation material to form a shallow trench isolation; exposing the conductive layer; and selectively removing the conductive layer to form a first conductive strap which forms the surface strap together with the conductive connection strap.
摘要翻译：一种形成表面带的方法包括：在其基板的表面上形成具有导电连接层的深沟槽电容器和与导电层接触的导电连接层; 形成覆盖所述焊盘层和所述导电连接层的多晶硅层; 以角度进行选择性离子注入，以使多晶硅层的一部分成为未掺杂的多晶硅层; 去除未掺杂的多晶硅层以暴露部分导电连接层; 蚀刻暴露的导电连接层以形成凹部; 去除所述多晶硅层以使所述暴露的导电连接层成为导电连接带; 用绝缘材料填充凹槽以形成浅沟槽隔离; 暴露导电层; 并且选择性地去除导电层以形成与导电连接带一起形成表面带的第一导电带。

9. 发明授权

US07535045B2 Checkerboard deep trench dynamic random access memory cell array layout 有权
标题翻译：棋盘深沟动态随机存取存储单元阵列布局
公开(公告)号：US07535045B2
公开(公告)日：2009-05-19
申请号：US11776558
申请日：2007-07-12
申请人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
发明人： Chien-Li Cheng , Chin-Tien Yang , Tzung-Han Lee , Shian-Hau Liao , Chung-Yuan Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/0207 , H01L27/10885 , H01L27/10888 , Y10S257/905 , Y10S257/906
摘要： A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.
摘要翻译：公开了一种棋盘深沟动态随机存取存储单元阵列布局，其包括衬底，设置在衬底上的多个栅极导体线，嵌入在栅极导体下方的衬底中的多个棋盘布置且交错的深沟槽电容器结构线路，以及形成在栅极导体线下方的基板中的多个有源区域，交替布置有深沟槽电容器结构，并与相邻的深沟槽电容器结构电连接。深沟槽电容器结构之上的栅极导体线的部分的宽度比在有源区上方的栅极导体线的部分的宽度窄。

10. 发明申请

US20060202248A1 SRAM cell structure and manufacturing method thereof 有权
公开(公告)号：US20060202248A1
公开(公告)日：2006-09-14
申请号：US11416926
申请日：2006-05-02
申请人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
发明人： Tzung-Han Lee , Kuang-Pi Lee , Wen-Jeng Lin , Rern-Hurng Larn
IPC分类号： H01L29/94
CPC分类号： H01L27/1087 , H01L27/11 , Y10S257/903
摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

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