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1. 发明授权

US10423216B2 Asymmetric multi-core processor with native switching mechanism 有权
公开(公告)号：US10423216B2
公开(公告)日：2019-09-24
申请号：US14077740
申请日：2013-11-12
申请人： VIA TECHNOLOGIES, INC.
发明人： Rodney E. Hooker , Terry Parks , G. Glenn Henry
IPC分类号： G06F9/46 , G06F1/3293 , G06F9/50
摘要： A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.

2. 发明授权

US10216520B2 Compressing instruction queue for a microprocessor 有权
公开(公告)号：US10216520B2
公开(公告)日：2019-02-26
申请号：US14569313
申请日：2014-12-12
申请人： VIA TECHNOLOGIES, INC.
发明人： Matthew Daniel Day , G. Glenn Henry , Terry Parks
IPC分类号： G06F9/38
摘要： A compressing instruction queue for a microprocessor including a storage queue and a redirect logic circuit. The storage queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic circuit is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the storage queue without leaving unused storage locations and beginning at a first available storage location in the storage queue. The redirect logic circuit performs redirection and compression to eliminate empty locations or holes in the storage queue and to reduce the number of write ports interfaced with each storage location of the storage queue.

3. 发明授权

US09798898B2 Microprocessor with secure execution mode and store key instructions 有权
公开(公告)号：US09798898B2
公开(公告)日：2017-10-24
申请号：US14884525
申请日：2015-10-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Brent Bean , Thomas A. Crispin
IPC分类号： G06F21/00 , G06F21/72 , G06F9/30 , H04L9/08 , G06F21/74 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/60 , G06F21/71 , H04L9/06
CPC分类号： G06F21/72 , G06F9/30003 , G06F9/30079 , G06F9/30178 , G06F9/30189 , G06F12/0875 , G06F21/52 , G06F21/54 , G06F21/602 , G06F21/71 , G06F21/74 , G06F2212/402 , G06F2212/452 , G06F2221/2107 , H04L9/0618 , H04L9/0827 , H04L9/0861 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/20
摘要： A microprocessor conditionally grants a request to switch from a normal execution mode in which encrypted instructions cannot be executed, into a secure execution mode (SEM). Thereafter, the microprocessor executes a plurality of instructions, including a store-key instruction to write a set of one or more cryptographic key values into a secure memory of the microprocessor. After fetching an encrypted program from an instruction cache, the microprocessor decrypts the encrypted program into plaintext instructions using decryption logic within the microprocessor's instruction-processing pipeline.

4. 发明申请

US20150067369A1 MULTI-CORE SYNCHRONIZATION MECHANISM 有权
标题翻译：多核同步机制
公开(公告)号：US20150067369A1
公开(公告)日：2015-03-05
申请号：US14281434
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F1/04 , G06F1/32
CPC分类号： G06F1/3287 , G06F1/04 , G06F1/32 , G06F9/522 , G06F12/0891 , G06F2212/1028 , G06F2212/60
摘要： A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.
摘要翻译：微处理器包括控制单元，该控制单元被配置为选择性地将各个时钟信号控制到多个处理核心中的每一个。每个处理核心被配置为分别向控制单元写入一个值。对于所述多个处理核心的每个核心，所述控制单元被配置为响应于所述核心向所述控制单元写入值而将相应的时钟信号关断到所述核心。控制单元被配置为检测当所有处理核心已经向控制单元写入值并且控制单元已经将各个时钟信号截止到所有处理核心时发生的状况。控制单元被配置为响应于检测到所发生的状况，同时将各个时钟信号接通到所有处理核心。

5. 发明申请

US20150067306A1 INTER-CORE COMMUNICATION VIA UNCORE RAM 有权
标题翻译：内核通信通过核心RAM
公开(公告)号：US20150067306A1
公开(公告)日：2015-03-05
申请号：US14281551
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Rodney E. Hooker , Stephan Gaskins
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes a plurality of processing cores and an uncore random access memory (RAM) readable and writable by each of the plurality of processing cores. Each core of the plurality of processing cores comprises microcode run by the core that implements architectural instructions of an instruction set architecture of the microprocessor. The microcode is configured to both read and write the uncore RAM to accomplish inter-core communication between the plurality of processing cores.
摘要翻译：微处理器包括多个处理核心和由多个处理核心中的每一个可读和写的非随机存取存储器（RAM）。多个处理核心的每个核心包括实现微处理器的指令集架构的架构指令的由核心运行的微代码。微码被配置为读取和写入非空白RAM以实现多个处理核之间的核心间通信。

6. 发明申请

US20150067215A1 MULTI-CORE SYNCHRONIZATION MECHANISM WITH INTERRUPTS ON SYNC CONDITION 有权
标题翻译：具有同步条件中断的多核同步机制
公开(公告)号：US20150067215A1
公开(公告)日：2015-03-05
申请号：US14281681
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F13/24
CPC分类号： G06F9/3885 , G06F1/04 , G06F1/12 , G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/30032 , G06F9/30047 , G06F9/30079 , G06F9/30087 , G06F9/30105 , G06F9/30145 , G06F9/3802 , G06F9/3861 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F9/4418 , G06F12/0808 , G06F12/084 , G06F12/0875 , G06F13/24 , G06F13/364 , G06F13/42 , G06F21/53 , G06F21/57 , G06F2212/452 , G06F2212/6028 , G06F2212/62 , H01L22/34 , H04L9/0877 , H04L9/0897 , Y02B70/12 , Y02B70/123 , Y02B70/126 , Y02B70/30 , Y02D10/10 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/171 , Y02D10/172 , Y02D10/30 , Y02D50/20
摘要： A microprocessor includes a plurality of processing cores, each comprising a respective interrupt request input and a control unit configured to receive a respective synchronization request from each of the plurality of processing cores. The control unit is configured to generate an interrupt request to all of the plurality of processing cores on their respective interrupt request inputs in response to detecting that the control unit has received the respective synchronization request from all of the plurality of processing cores.
摘要翻译：微处理器包括多个处理核，每个处理核包括相应的中断请求输入和被配置为从多个处理核中的每一个接收相应的同步请求的控制单元。控制单元被配置为响应于检测到控制单元已经从所有多个处理核心中接收到相应的同步请求而在其各自的中断请求输入端上产生对所有多个处理核心的中断请求。

7. 发明申请

US20140298060A1 ASYMMETRIC MULTI-CORE PROCESSOR WITH NATIVE SWITCHING MECHANISM 有权
标题翻译：不对称多核心处理器与本地切换机制
公开(公告)号：US20140298060A1
公开(公告)日：2014-10-02
申请号：US14077740
申请日：2013-11-12
申请人： VIA TECHNOLOGIES, INC.
发明人： Rodney E. Hooker , Terry Parks , G. Glenn Henry
IPC分类号： G06F1/32
摘要： A processor includes first and second processing cores configured to support first and second respective subsets of features of its instruction set architecture (ISA) feature set. The first subset is less than all the features of the ISA feature set. The first and second subsets are different but their union is all the features of the ISA feature set. The first core detects a thread, while being executed by the first core rather than by the second core, attempted to employ a feature not in the first subset and, in response, to indicate a switch from the first core to the second core to execute the thread. The unsupported feature may be an unsupported instruction or operating mode. A switch may also be made if the lower performance/power core is being over-utilized or the higher performance/power core is being under-utilized.
摘要翻译：处理器包括被配置为支持其指令集体系结构（ISA）特征集的特征的第一和第二相应子集的第一和第二处理核心。第一个子集小于ISA功能集的所有功能。第一个和第二个子集是不同的，但它们的联合是ISA功能集的所有功能。第一核心在由第一核心而不是第二核心执行的同时检测线程，尝试使用不在第一子集中的特征，并且响应地指示从第一核到第二核的切换以执行线程。不支持的功能可能是不支持的指令或操作模式。如果较低性能/功率核心被过度利用或较高性能/功率核心利用不足，也可能产生开关。

8. 发明申请

US20140059358A1 REVOKEABLE MSR PASSWORD PROTECTION 有权
标题翻译：可靠的MSR密码保护
公开(公告)号：US20140059358A1
公开(公告)日：2014-02-27
申请号：US14053953
申请日：2013-10-15
申请人： VIA Technologies, Inc.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F9/30076 , G06F9/30101 , G06F21/31 , G06F21/71 , G06F21/78 , G06F21/79
摘要： A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key.
摘要翻译：微处理器包括具有地址的型号特定寄存器（MSR），具有第一预定值制造的保险丝和控制寄存器。微处理器首先将第一预定值从保险丝加载到控制寄存器中。在最初将第一预定值加载到控制寄存器之后，微处理器还从包括微处理器的计算机系统的系统软件接收第二预定值。微处理器通过提供通过利用在微处理器的第一实例中制造的秘密密钥加密第一预定值和MSR地址的功能产生的第一密码的指令来禁止对MSR的访问，并使得能够通过指令访问MSR 其提供通过用秘密密钥加密第二预定值的功能和MSR地址产生的第二密码。

9. 发明授权

US10198269B2 Dynamic reconfiguration of multi-core processor 有权
公开(公告)号：US10198269B2
公开(公告)日：2019-02-05
申请号：US14281657
申请日：2014-05-19
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn Henry , Terry Parks , Darius D. Gaskins
IPC分类号： G06F9/44 , G06F1/32 , G06F9/38 , G06F12/084 , G06F13/24 , G06F9/4401 , G06F13/364 , G06F12/0808 , G06F9/30 , G06F12/0875 , G06F1/04 , G06F1/12 , G06F13/42 , G06F21/53 , G06F21/57 , H04L9/08 , H01L21/66
摘要： A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

10. 发明授权

US09442732B2 Running state power saving via reduced instructions per clock operation 有权
标题翻译：通过每个时钟操作减少指令来运行状态省电
公开(公告)号：US09442732B2
公开(公告)日：2016-09-13
申请号：US13777104
申请日：2013-02-26
申请人： VIA Technologies, Inc.
发明人： G. Glenn Henry , Terry Parks
IPC分类号： G06F9/30 , G06F1/32
CPC分类号： G06F9/30189 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/329 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/24
摘要： A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states.
摘要翻译：微处理器包括可写的功能单元和控制寄存器，以使功能单元执行动作，以减少微处理器的每时钟指令速率，以在微处理器以最低性能运行状态运行时降低功耗。这些操作的示例包括按顺序执行，无序执行，串行与并行缓存访问以及每个时钟周期中的单个或多个指令发出，退出，转换和/或格式化。只有在存在附加条件的情况下，才能设置动作，例如最低运行时间停留在最低运行状态，不超过最长时间运行在较高的运行状态，用户没有禁用该功能，微处理器支持多个运行状态和操作系统支持多个运行状态。

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