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1. 发明授权

US07937647B2 Error-detecting and correcting FPGA architecture 有权
标题翻译：错误检测和校正FPGA架构
公开(公告)号：US07937647B2
公开(公告)日：2011-05-03
申请号：US11829335
申请日：2007-07-27
申请人： Vidyadhara Bellipaddy , Gregory Bakker
发明人： Vidyadhara Bellipaddy , Gregory Bakker
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03K19/1776 , G06F11/1052 , G11C2029/0411 , H03K19/17764
摘要： A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.
摘要翻译：提供了用于纠错FPGA的方法和装置。生成用于配置的ECC数据并将其编程到配置存储器中的ECC行中。在引导时，确定是否设置完整性校验位。如果是这样，则执行完整性检查。如果检测到单位错误，如果位错误是错误的“0”值，则包含错误“0”值的存储器位置被重新编程为“1”值。如果位错误是错误的“1”值，则存储器块数据被保存在非易失性存储器块中，包含该错误的配置存储器块被擦除并且使用校正位被重新编程。如果存在多个错误，则设置错误标志。用户通过JTAG端口读取错误标志的状态。如果设置了错误标志，则启动完整的重新编程周期。

2. 发明申请

US20090031194A1 ERROR-DETECTING AND CORRECTING FPGA ARCHITECTURE 有权
标题翻译：错误检测和校正FPGA架构
公开(公告)号：US20090031194A1
公开(公告)日：2009-01-29
申请号：US11829335
申请日：2007-07-27
申请人： Vidyadhara Bellipaddy , Gregory Bakker
发明人： Vidyadhara Bellipaddy , Gregory Bakker
IPC分类号： G11C29/00
CPC分类号： H03K19/1776 , G06F11/1052 , G11C2029/0411 , H03K19/17764
摘要： A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.
摘要翻译：提供了用于纠错FPGA的方法和装置。生成用于配置的ECC数据并将其编程到配置存储器中的ECC行中。在引导时，确定是否设置完整性校验位。如果是这样，则执行完整性检查。如果检测到单位错误，如果位错误是错误的“0”值，则包含错误“0”值的存储器位置被重新编程为“1”值。如果位错误是错误的“1”值，则存储器块数据被保存在非易失性存储器块中，包含该错误的配置存储器块被擦除并且使用校正位被重新编程。如果存在多个错误，则设置错误标志。用户通过JTAG端口读取错误标志的状态。如果设置了错误标志，则启动完整的重新编程周期。

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