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1. 发明授权

US07937647B2 Error-detecting and correcting FPGA architecture 有权
标题翻译：错误检测和校正FPGA架构
公开(公告)号：US07937647B2
公开(公告)日：2011-05-03
申请号：US11829335
申请日：2007-07-27
申请人： Vidyadhara Bellipaddy , Gregory Bakker
发明人： Vidyadhara Bellipaddy , Gregory Bakker
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03K19/1776 , G06F11/1052 , G11C2029/0411 , H03K19/17764
摘要： A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.
摘要翻译：提供了用于纠错FPGA的方法和装置。生成用于配置的ECC数据并将其编程到配置存储器中的ECC行中。在引导时，确定是否设置完整性校验位。如果是这样，则执行完整性检查。如果检测到单位错误，如果位错误是错误的“0”值，则包含错误“0”值的存储器位置被重新编程为“1”值。如果位错误是错误的“1”值，则存储器块数据被保存在非易失性存储器块中，包含该错误的配置存储器块被擦除并且使用校正位被重新编程。如果存在多个错误，则设置错误标志。用户通过JTAG端口读取错误标志的状态。如果设置了错误标志，则启动完整的重新编程周期。

2. 发明申请

US20090031194A1 ERROR-DETECTING AND CORRECTING FPGA ARCHITECTURE 有权
标题翻译：错误检测和校正FPGA架构
公开(公告)号：US20090031194A1
公开(公告)日：2009-01-29
申请号：US11829335
申请日：2007-07-27
申请人： Vidyadhara Bellipaddy , Gregory Bakker
发明人： Vidyadhara Bellipaddy , Gregory Bakker
IPC分类号： G11C29/00
CPC分类号： H03K19/1776 , G06F11/1052 , G11C2029/0411 , H03K19/17764
摘要： A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.
摘要翻译：提供了用于纠错FPGA的方法和装置。生成用于配置的ECC数据并将其编程到配置存储器中的ECC行中。在引导时，确定是否设置完整性校验位。如果是这样，则执行完整性检查。如果检测到单位错误，如果位错误是错误的“0”值，则包含错误“0”值的存储器位置被重新编程为“1”值。如果位错误是错误的“1”值，则存储器块数据被保存在非易失性存储器块中，包含该错误的配置存储器块被擦除并且使用校正位被重新编程。如果存在多个错误，则设置错误标志。用户通过JTAG端口读取错误标志的状态。如果设置了错误标志，则启动完整的重新编程周期。

3. 发明授权

US07911226B2 Power-up and power-down circuit for system-on-a-chip integrated circuit 有权
标题翻译：用于片上系统集成电路的上电和掉电电路
公开(公告)号：US07911226B2
公开(公告)日：2011-03-22
申请号：US11467279
申请日：2006-08-25
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H03K19/173 , G05F1/00 , G05F5/00
CPC分类号： G11C5/147 , H01L2924/0002 , H03K17/22 , Y10T307/50 , Y10T307/724 , H01L2924/00
摘要： A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
摘要翻译：用于集成电路的上电和掉电电路包括用于第一电压的电压调节器。第一个I / O焊盘内部耦合到电压调节器和第一个内部电路的输入端。第二电压外部耦合到第一I / O焊盘。第二I / O焊盘内部耦合到被配置为驱动外部晶体管的基极的电压调节器的输出端。集成电路的第三个I / O焊盘内部耦合到电压调节器的参考电压输入端。第四I / O焊盘耦合到电压调节器的反馈输入端。集成电路的第五个I / O焊盘内部耦合到逻辑电路，该逻辑电路从包括设置在集成电路上的实时时钟电路的内部信号的内部信号控制集成电路的上电和掉电。

4. 发明申请

US20100156457A1 PLD PROVIDING SOFT WAKEUP LOGIC 有权
标题翻译： PLD提供软件唤醒逻辑
公开(公告)号：US20100156457A1
公开(公告)日：2010-06-24
申请号：US12340358
申请日：2008-12-19
申请人： Jonathan W. Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
发明人： Jonathan W. Greene , Gregory Bakker , Vidyadhara Bellippady , Volker Hecht , Theodore Speers
IPC分类号： H03K19/177 , H03K19/0175
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译：公开了具有多个可编程区域的可编程逻辑器件（PLD）。一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

5. 发明授权

US07683660B1 Programmable logic device with a microcontroller-based control system 有权
标题翻译：可编程逻辑器件，具有基于微控制器的控制系统
公开(公告)号：US07683660B1
公开(公告)日：2010-03-23
申请号：US12023299
申请日：2008-01-31
申请人： Gregory Bakker , Joel Landry , William C. Plants
发明人： Gregory Bakker , Joel Landry , William C. Plants
IPC分类号： H03K19/173
CPC分类号： H03K19/1733 , G06F17/5054
摘要： A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block. The programmable logic integrated circuit device, comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.
摘要翻译：公开了一种用于可编程逻辑集成电路装置中基于微控制器的控制系统的计算机可读介质中的计算机程序产品。计算机程序产品包括用于初始化设备的第一指令，用于从可编程逻辑集成电路器件外部的数据源读取编程数据的第二指令，用于将编程数据传送到可编程逻辑集成电路器件内部的控制元件的第三指令。规定了第四条指令，用于将编程到可编程逻辑集成电路设备中的用户逻辑的内部逻辑状态的至少一部分保存到非易失性存储器块中，以及用于恢复内部逻辑的至少一部分的第五指令从非易失性存储器块编程到可编程逻辑集成电路器件中的用户逻辑状态。可编程逻辑集成电路器件包括微控制器模块和具有编程电路的可编程逻辑模块，并且具有将微控制器模块耦合到编程电路的子总线。

6. 发明授权

US07579895B2 Clock-generator architecture for a programmable-logic-based system on a chip 有权
标题翻译：用于芯片上基于可编程逻辑的系统的时钟发生器架构
公开(公告)号：US07579895B2
公开(公告)日：2009-08-25
申请号：US11932807
申请日：2007-10-31
申请人： Shin-Nan Sun , Limin Zhu , Theodore Speers , Gregory Bakker
发明人： Shin-Nan Sun , Limin Zhu , Theodore Speers , Gregory Bakker
IPC分类号： H03K17/62
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.
摘要翻译：一种可编程片上系统集成电路器件，包括晶体振荡器电路，RC振荡器电路和外部振荡器输入中的至少一个。时钟调理电路选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。实时时钟可选择性地耦合到可编程逻辑块，晶体振荡器电路，RC振荡器电路和外部振荡器输入之一。可编程逻辑块耦合到时钟调节电路和实时时钟。

7. 发明授权

US07560954B2 Programmable system on a chip for temperature monitoring and control 有权
标题翻译：片上可编程系统进行温度监控
公开(公告)号：US07560954B2
公开(公告)日：2009-07-14
申请号：US12178874
申请日：2008-07-24
申请人： Rabindranath Balasubramanian , Limin Zhu , Gregory Bakker
发明人： Rabindranath Balasubramanian , Limin Zhu , Gregory Bakker
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.
摘要翻译：可编程片上系统集成电路器件包括可编程逻辑块，至少一个用户非易失性存储器块，以及在单个半导体集成电路芯片或倒装芯片上的温度感测和控制模拟和数字电路面对或其他多模配置。具有温度测量和控制电路的可编程片上系统芯片集成电路执行温度测量和控制功能，可用于创建片上温度记录。

8. 发明授权

US07493506B2 Programmable system on a chip for power-supply voltage and current monitoring and control 有权
标题翻译：芯片上的可编程系统，用于电源电压和电流监控
公开(公告)号：US07493506B2
公开(公告)日：2009-02-17
申请号：US11932778
申请日：2007-10-31
申请人： Rabindranth Balasubramanian , Gregory Bakker
发明人： Rabindranth Balasubramanian , Gregory Bakker
IPC分类号： G06F1/26
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.
摘要翻译：可编程片上系统芯片集成电路器件包括可编程逻辑块，至少一个用户非易失性存储器块，以及在单个半导体集成电路芯片或倒装芯片上的电压测量和控制模拟和数字电路，面对面或其他多芯片配置。具有电压测量，电流测量和控制电路的可编程片上系统芯片集成电路执行电压测量和控制功能，可用于控制和监视连接到外部负载的外部电源。

9. 发明申请

US20080284532A1 VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT 审中-公开
标题翻译：电压和温度补偿RC振荡器电路
公开(公告)号：US20080284532A1
公开(公告)日：2008-11-20
申请号：US12182329
申请日：2008-07-30
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H03K3/26 , H03K3/02 , H03K3/42 , H03L1/00
CPC分类号： H03K3/0231 , H03K3/011 , H03L1/022
摘要： An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.
摘要翻译：集成温度补偿RC振荡器电路包括具有输入和输出的反相器。 RC网络耦合在逆变器和一对比较器之间。第一比较器具有耦合到第一参考电压的反相输入，耦合到RC网络的非反相输入和输出。第二比较器具有耦合到RC网络的反相输入，耦合到第二参考电压的非反相输入和输出。设置复位触发器具有耦合到第一比较器的输出的设置输入，耦合到第二比较器的输出的复位输入和耦合到反相器的输入的输出。比较器中的差分放大器各自具有二极管连接的p沟道MOS晶体管，其控制沟道宽度小于二极管连接的p沟道电流镜晶体管的p沟道MOS晶体管。

10. 发明授权

US07443198B1 Non-volatile look-up table for an FPGA 失效
标题翻译： FPGA的非易失性查找表
公开(公告)号：US07443198B1
公开(公告)日：2008-10-28
申请号：US11929287
申请日：2007-10-30
申请人： John McCollum , Gregory Bakker , Jonathan Greene
发明人： John McCollum , Gregory Bakker , Jonathan Greene
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1778 , H03K19/17728
摘要： A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A one input non-volatile-memory-transistor based lookup table is coupled to each of the n data inputs of the multiplexer. The multiplexer has X inputs wherein n=2X as is known in the art. A sense amplifier is coupled to the output of the multiplexer.
摘要翻译：用于FPGA的基于非易失性存储器晶体管的查找表包括n：1多路复用器。一个输入非易失性存储器 - 晶体管的查找表被耦合到多路复用器的每个n个数据输入端。多路复用器具有如本领域已知的具有n = 2×X的X个输入。读出放大器耦合到多路复用器的输出端。

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