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1. 发明授权

US07961123B2 Time-interleaved analog-to-digital converter 有权
标题翻译：时间交织的模数转换器
公开(公告)号：US07961123B2
公开(公告)日：2011-06-14
申请号：US12575337
申请日：2009-10-07
申请人： Viswanathan Nagarajan , Sriram Murali , Sthanunathan Ramakrishnan , Visvesvaraya Pentakota , Jaiganesh Balakrishnan
发明人： Viswanathan Nagarajan , Sriram Murali , Sthanunathan Ramakrishnan , Visvesvaraya Pentakota , Jaiganesh Balakrishnan
IPC分类号： H03M1/06
CPC分类号： H03M1/1057 , H03M1/0836 , H03M1/1215
摘要： A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.
摘要翻译：提供了时间交织（TI）模数转换器（ADC）。 TI ADC通常包括时钟发生器，两个或更多个ADC，可调延迟元件和估计器。时钟发生器产生时钟信号。每个ADC与至少一个时钟信号相关联，以便在采样时刻对通常为宽静态的输入信号进行采样，其中相关函数存在于两个或更多个ADC之间的样本之间，该两个或更多个ADC是相关抽样时间之间的时间差异。估计器耦合到每个可调节延迟元件和每个ADC，以便计算相关函数，并且至少部分地基于相关函数来调整可调延迟元件以考虑ADC之间的采样失配。

2. 发明申请

US20110006933A1 TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：时间隔离的模拟数字转换器
公开(公告)号：US20110006933A1
公开(公告)日：2011-01-13
申请号：US12575337
申请日：2009-10-07
申请人： Viswanathan Nagarajan , Sriram Murali , Sthanunathan Ramakrishnan , Visvesvaraya Pentakota , Jaiganesh Balakrishnan
发明人： Viswanathan Nagarajan , Sriram Murali , Sthanunathan Ramakrishnan , Visvesvaraya Pentakota , Jaiganesh Balakrishnan
IPC分类号： H03M1/06 , H03M1/66
CPC分类号： H03M1/1057 , H03M1/0836 , H03M1/1215
摘要： A time-interleaved (TI) analog-to-digital converter (ADC) is provided. The TI ADC generally comprises a clock generator, two or more ADCs, adjustable delay elements, and an estimator. The clock generator generates clock signals. Each ADC is associated with at least one of the clock signals so as to sample an input signal that is generally wide-sense stationary at sampling instants, where correlation function exist between samples from a two or more of the ADCs that is a function of the time differences between associated sampling instants. The estimator is coupled to each of the adjustable delay elements and each of the ADCs so as to calculate the correlation function and adjust the adjustable delay elements to account for sampling mismatch between the ADCs based at least in part on the correlation function.
摘要翻译：提供了时间交织（TI）模数转换器（ADC）。 TI ADC通常包括时钟发生器，两个或更多个ADC，可调延迟元件和估计器。时钟发生器产生时钟信号。每个ADC与至少一个时钟信号相关联，以便在采样时刻对通常为宽静态的输入信号进行采样，其中相关函数存在于两个或更多个ADC之间的样本之间，该两个或更多个ADC是相关抽样时间之间的时间差异。估计器耦合到每个可调节延迟元件和每个ADC，以便计算相关函数，并且至少部分地基于相关函数来调整可调延迟元件以考虑ADC之间的采样失配。

3. 发明申请

US20100036460A1 PARALLEL SEARCH CIRCUIT FOR A MEDICAL IMPLANT RECEIVER 审中-公开
标题翻译：用于医疗植入物接收器的并行搜索电路
公开(公告)号：US20100036460A1
公开(公告)日：2010-02-11
申请号：US12536562
申请日：2009-08-06
申请人： Sthanunathan Ramakrishnan , Jawaharlal Tangudu , Visvesvaraya Pentakota
发明人： Sthanunathan Ramakrishnan , Jawaharlal Tangudu , Visvesvaraya Pentakota
IPC分类号： A61N1/08 , H04B1/16
CPC分类号： A61N1/3727
摘要： Parallel search circuit for a medical implant receiver. The circuit includes a radio frequency receiver that receives a first set of contents of a band of channels. The circuit also includes a processing circuit coupled to the radio frequency receiver to process in parallel a second set of contents of a plurality of channels of the band of channels and to detect a signal in the band of channels.
摘要翻译：用于医疗植入物接收器的并行搜索电路。该电路包括接收频道频带的第一组内容的射频接收机。电路还包括耦合到射频接收机的处理电路并行处理频道频带的多个信道的第二组内容并且检测频道频带中的信号。

4. 发明授权

US08390488B2 Non-linearity correction that is independent of input common mode, temperature variation, and process variation 有权
标题翻译：独立于输入共模，温度变化和工艺变化的非线性校正
公开(公告)号：US08390488B2
公开(公告)日：2013-03-05
申请号：US13196628
申请日：2011-08-02
申请人： Ganesh Kiran , Visvesvaraya Pentakota , Viswanathan Nagarajan
发明人： Ganesh Kiran , Visvesvaraya Pentakota , Viswanathan Nagarajan
IPC分类号： H03M1/06
CPC分类号： G11C27/02 , H03M1/0612 , H03M1/164 , H03M1/44
摘要： In pipeline analog-to-digital converters (ADCs) the third harmonic can degrade the performance of the ADC, and conventional circuits that attempt to cancel this third harmonic are oftentimes sensitive to process variation, temperature variation, and common mode variations. Here a correction circuit is provided that includes a compensator that adjusts control voltages for MOS capacitors to generally ensures that the difference between the gate-source voltages and threshold voltages of MOS capacitors is generally maintained across variations of process, temperature, and common mode.
摘要翻译：在管线模数转换器（ADC）中，三次谐波可能会降低ADC的性能，而试图消除此三次谐波的常规电路通常对工艺变化，温度变化和共模变化敏感。这里提供了一种校正电路，其包括调整MOS电容器的控制电压的补偿器，以通常确保MOS电容器的栅极 - 源极电压和阈值电压之间的差异通常保持在过程，温度和共模的变化。

5. 发明授权

US08742845B2 Amplifier circuits with reduced power consumption 有权
标题翻译：具有降低功耗的放大器电路
公开(公告)号：US08742845B2
公开(公告)日：2014-06-03
申请号：US13476330
申请日：2012-05-21
申请人： Shagun Dusad , Lokesh Kumar Gupta , Visvesvaraya Pentakota
发明人： Shagun Dusad , Lokesh Kumar Gupta , Visvesvaraya Pentakota
IPC分类号： H03F3/45
CPC分类号： H03F3/45 , H03F3/45188 , H03F2203/45352 , H03F2203/45362
摘要： Various embodiments of an amplifier circuit are provided. In one embodiment, the amplifier circuit includes an input differential circuitry configured to convert a pair of input differential voltage signals to a pair of differential current signals. The amplifier circuit includes a cascode circuitry operable to mirror the pair of differential current signals received from the first output terminal and the second output terminal to an output terminal of the first cascode transistor and an output terminal of the second cascode transistor. The amplifier circuit includes a current control circuit operable to divert an amount of bias current to reduce a current through the cascode circuitry, to thereby reduce a load of the amplifier circuit, the reduction in the load of the amplifier circuit allowing a reduction in current through the input differential circuitry for maintaining a predetermined bandwidth of the amplifier circuit.
摘要翻译：提供了放大器电路的各种实施例。在一个实施例中，放大器电路包括被配置为将一对输入差分电压信号转换成一对差分电流信号的输入差分电路。放大器电路包括共源共栅电路，其可操作以将从第一输出端和第二输出端接收的一对差分电流信号镜像到第一共源共栅晶体管的输出端和第二共源共栅晶体管的输出端。放大器电路包括电流控制电路，其可操作以转移一定量的偏置电流以减少通过共源共栅电路的电流，从而减小放大器电路的负载，放大器电路的负载的减小允许电流通过用于维持放大器电路的预定带宽的输入差分电路。

6. 发明申请

US20130307623A1 Amplifier Circuits with Reduced Power Consumption 有权
标题翻译：具有降低功耗的放大器电路
公开(公告)号：US20130307623A1
公开(公告)日：2013-11-21
申请号：US13476330
申请日：2012-05-21
申请人： Shagun Dusad , Lokesh Kumar Gupta , Visvesvaraya Pentakota
发明人： Shagun Dusad , Lokesh Kumar Gupta , Visvesvaraya Pentakota
IPC分类号： H03F3/45
CPC分类号： H03F3/45 , H03F3/45188 , H03F2203/45352 , H03F2203/45362
摘要： Various embodiments of an amplifier circuit are provided. In one embodiment, the amplifier circuit includes an input differential circuitry configured to convert a pair of input differential voltage signals to a pair of differential current signals. The amplifier circuit includes a cascode circuitry operable to mirror the pair of differential current signals received from the first output terminal and the second output terminal to an output terminal of the first cascode transistor and an output terminal of the second cascode transistor. The amplifier circuit includes a current control circuit operable to divert an amount of bias current to reduce a current through the cascode circuitry, to thereby reduce a load of the amplifier circuit, the reduction in the load of the amplifier circuit allowing a reduction in current through the input differential circuitry for maintaining a predetermined bandwidth of the amplifier circuit.
摘要翻译：提供了放大器电路的各种实施例。在一个实施例中，放大器电路包括被配置为将一对输入差分电压信号转换成一对差分电流信号的输入差分电路。放大器电路包括共源共栅电路，其可操作以将从第一输出端和第二输出端接收的一对差分电流信号镜像到第一共源共栅晶体管的输出端和第二共源共栅晶体管的输出端。放大器电路包括电流控制电路，其可操作以转移一定量的偏置电流以减少通过共源共栅电路的电流，从而减小放大器电路的负载，放大器电路的负载的减小允许电流通过用于维持放大器电路的预定带宽的输入差分电路。

7. 发明授权

US08188902B2 Ternary search SAR ADC 有权
标题翻译：三进制搜索SAR ADC
公开(公告)号：US08188902B2
公开(公告)日：2012-05-29
申请号：US12858104
申请日：2010-08-17
申请人： Yujendara Mitikiri , Visvesvaraya Pentakota
发明人： Yujendara Mitikiri , Visvesvaraya Pentakota
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/468
摘要： Traditionally, successive approximation register (SAR) analog-to-digital converters (ADCs) using binary search algorithms have consumed power by performing unnecessary switching of a capacitive digital-to-analog converter (CDAC) when a CDAC voltage is relatively close to a sampling analog input signal. Here, a SAR ADC is provided that reduces the number of switching events. To accomplish this, a multi-stage comparator is provided that generates multiple output signals for SAR logic. Based on these outputs, the SAR logic can more efficiently switch its CDAC using a ternary search algorithm to reduce power consumption and improve efficiency.
摘要翻译：传统上，使用二进制搜索算法的逐次逼近寄存器（SAR）模数转换器（ADC）通过在CDAC电压相对接近采样时执行电容性数模转换器（CDAC）的不必要的切换来消耗功率模拟输入信号。这里，提供了一个减少开关事件数量的SAR ADC。为了实现这一点，提供了多级比较器，其产生用于SAR逻辑的多个输出信号。基于这些输出，SAR逻辑可以使用三元搜索算法更有效地切换其CDAC，以降低功耗并提高效率。

8. 发明申请

US20070024485A1 Reducing Variation in Reference Voltage When the Load Varies Dynamically 有权
标题翻译：当负载动态变化时，减小参考电压的变化
公开(公告)号：US20070024485A1
公开(公告)日：2007-02-01
申请号：US11161253
申请日：2005-07-28
申请人： Abhaya Kumar , Visvesvaraya Pentakota
发明人： Abhaya Kumar , Visvesvaraya Pentakota
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/145
摘要： Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.
摘要翻译：从通过路径连接的参考缓冲器向组件提供基本恒定的参考电压。估计将在期望的持续时间内提供给参考缓冲器的负载，并且向路径添加虚拟负载，使得路径上的总负载近似恒定。在ADC的阶段的情况下，在采样阶段期间由每个级产生的子代码用于估计将要提供的负载，并且将虚拟负载添加到保持阶段以保持参考电压恒定在保持阶段，根据需要。

9. 发明申请

US20050104760A1 Applying desired voltage at a node 有权
公开(公告)号：US20050104760A1
公开(公告)日：2005-05-19
申请号：US10706029
申请日：2003-11-13
申请人： Visvesvaraya Pentakota
发明人： Visvesvaraya Pentakota
IPC分类号： H03M1/06 , H03M1/12 , H03M1/34 , H03M1/78
CPC分类号： H03M1/06 , H03M1/12
摘要： To apply a desired voltage at a node driving a load impedance, a voltage source providing the desired voltage is connected to the node. In addition, a current source supplying an amount of current that would be drawn by the impedance if the voltage source alone were connected across the impedance. As a result, the voltage source may be freed substantially from supplying current, which may be advantageously used in several situations. For example, the approach can be used to connect a voltage source directly to a high load without potentially requiring a buffer between the voltage source and the node. Alternatively, the approach can be used to apply the same desired voltage at each of multiple nodes connected in series using the same voltage source without being affected by the routing resistance generally present between each pair of the nodes.

10. 发明申请

US20070085580A1 Generating Multiple Delayed Signals of Different Phases from a Reference Signal Using Delay Locked Loop (DLL) 有权
标题翻译：使用延迟锁定环（DLL）从参考信号生成不同相位的多个延迟信号
公开(公告)号：US20070085580A1
公开(公告)日：2007-04-19
申请号：US11163319
申请日：2005-10-14
申请人： Ramesh Singh , Visvesvaraya Pentakota , Abhaya Kumar , Chun Lee
发明人： Ramesh Singh , Visvesvaraya Pentakota , Abhaya Kumar , Chun Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/095 , H03M1/164 , H03M1/44
摘要： A delay locked loop (DLL) circuit in which situations of lock to multiple periods of a reference signal is determined by a lock detector using dummy delay elements and a duty cycle correction circuit (DCC). The lock detector, the dummy delay elements and the delay control circuit are used in a path parallel to the delay elements which generate the desired delayed signals having different delays in relation to the reference signal. Due to the use of the parallel path, the throughput performance of the DLL circuit is not impeded. In an embodiment, separate charge pumps are used by a phase comparator and the lock detector used in the parallel path.
摘要翻译：延迟锁定环（DLL）电路，其中锁定到参考信号的多个周期的情况由使用伪延迟元件的锁定检测器和占空比校正电路（DCC）确定。锁定检测器，虚拟延迟元件和延迟控制电路在与延迟元件平行的路径中使用，所述延迟元件产生相对于参考信号具有不同延迟的所需延迟信号。由于使用并行路径，DLL电路的吞吐量性能不受阻碍。在一个实施例中，分离的电荷泵由相位比较器和在并行路径中使用的锁定检测器使用。

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