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1. 发明申请

US20120298965A1 MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION 有权
标题翻译：具有电沉积金属沉积的多孔结构
公开(公告)号：US20120298965A1
公开(公告)日：2012-11-29
申请号：US13568839
申请日：2012-08-07
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/772 , B82Y99/00
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.
摘要翻译：一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

2. 发明申请

US20120132989A1 MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION 有权
公开(公告)号：US20120132989A1
公开(公告)日：2012-05-31
申请号：US12955388
申请日：2010-11-29
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

3. 发明授权

US09099327B2 Multigate structure formed with electroless metal deposition 有权
标题翻译：用无电金属沉积形成多孔结构
公开(公告)号：US09099327B2
公开(公告)日：2015-08-04
申请号：US13568839
申请日：2012-08-07
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/06 , H01L21/8238 , H01L29/417
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.
摘要翻译：一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

4. 发明授权

US08936978B2 Multigate structure formed with electroless metal deposition 有权
公开(公告)号：US08936978B2
公开(公告)日：2015-01-20
申请号：US12955388
申请日：2010-11-29
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/06 , H01L29/417
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

5. 发明授权

US08741753B2 Use of band edge gate metals as source drain contacts 有权
标题翻译：使用带边栅极金属作为源极漏极触点
公开(公告)号：US08741753B2
公开(公告)日：2014-06-03
申请号：US13611736
申请日：2012-09-12
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20 , H01L21/3205 , H01L21/00
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
摘要翻译：一种器件包括形成在半导体衬底中的沟道上方的栅叠层。栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。该装置还包括邻近通道的源极和漏极接触。源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

6. 发明申请

US20130241008A1 Use of Band Edge Gate Metals as Source Drain Contacts 有权
标题翻译：使用带边缘栅极金属作为源极漏极触点
公开(公告)号：US20130241008A1
公开(公告)日：2013-09-19
申请号：US13611736
申请日：2012-09-12
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
摘要翻译：一种器件包括形成在半导体衬底中的沟道上方的栅叠层。栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。该装置还包括邻近通道的源极和漏极接触。源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

7. 发明申请

US20130241007A1 USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS 审中-公开
标题翻译：使用带边缘金属作为源漏联系
公开(公告)号：US20130241007A1
公开(公告)日：2013-09-19
申请号：US13421276
申请日：2012-03-15
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described.
摘要翻译：一种方法包括提供具有有意掺杂的表面区域的半导体衬底，有意掺杂的表面区域对应于晶体管的源极和漏极的位置; 在晶体管的栅极区域中的栅绝缘体层上沉积带边缘栅极金属层，同时将带边缘栅极金属沉积到半导体衬底的表面上以与有意掺杂的表面区域接触; 以及在所述栅极区域中以及所述源极和漏极的位置中的所述带边缘栅极金属之上沉积接触金属层。源极/漏极区域中的带边缘栅极金属降低了晶体管的源极/漏极接触的肖特基势垒高度，并且用于降低接触电阻。还描述了根据该方法制造的晶体管。

8. 发明授权

US06444578B1 Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices 有权
标题翻译：用于减少浅结和薄SOI电子器件中Si消耗的自对准硅化物工艺
公开(公告)号：US06444578B1
公开(公告)日：2002-09-03
申请号：US09791024
申请日：2001-02-21
申请人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
发明人： Cyril Cabral, Jr. , Roy Arthur Carruthers , Kevin K. Chan , Guy M. Cohen , Kathryn Wilder Guarini , James M. Harper , Christian Lavoie , Paul M. Solomon
IPC分类号： H01L2144
CPC分类号： H01L21/28518
摘要： The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.
摘要翻译：本发明涉及在采用M-Si或M-Si-Ge合金的自对准硅化物工艺中降低Si消耗的方法，其中M是Co，Ni或CoNi以及Si的覆盖层。本发明特别可用于最大限度地减少浅结和薄绝缘体上硅（SOI）电子器件中的Si消耗。

9. 发明申请

US20120292677A1 FERROELECTRIC SEMICONDUCTOR TRANSISTOR DEVICES HAVING GATE MODULATED CONDUCTIVE LAYER 有权
标题翻译：具有门控调制导电层的电磁半导体晶体管器件
公开(公告)号：US20120292677A1
公开(公告)日：2012-11-22
申请号：US13108340
申请日：2011-05-16
申请人： Catherine A. Dubourdieu , David J. Frank , Martin M. Frank , Vijay Narayanan , Paul M. Solomon , Thomas N. Theis
发明人： Catherine A. Dubourdieu , David J. Frank , Martin M. Frank , Vijay Narayanan , Paul M. Solomon , Thomas N. Theis
IPC分类号： H01L29/772
CPC分类号： H01L29/4232 , H01L29/42316 , H01L29/812
摘要： Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.
摘要翻译：提供了铁电半导体开关器件，包括具有栅极叠层结构的场效应晶体管（FET）器件，栅极堆叠结构形成有设置在栅极接触和薄导电层（量子导电层）之间的铁电层。栅极接触和铁电层用于调制薄导电层的有效功函数。具有调制功函数的薄导电层耦合到半导体沟道层，以调制通过半导体的电流，并实现陡峭的子阈值斜率。

10. 发明授权

US08283703B2 Solid state Klystron 有权
标题翻译：固态速调管
公开(公告)号：US08283703B2
公开(公告)日：2012-10-09
申请号：US11870875
申请日：2007-10-11
申请人： Paul M. Solomon
发明人： Paul M. Solomon
IPC分类号： H01L27/148
CPC分类号： H01J25/10 , B82Y10/00
摘要： A solid state Klystron structure is fabricated by forming a source contact and a drain contact to both ends of a conducting wire and by forming a bias gate and a signal gate on the conducting wire. The conducting wire may be at least one carbon nanotube or at least one semiconductor wire with long ballistic mean free paths. By applying a signal at a frequency that corresponds to an integer multiple of the transit time of the ballistic carriers between adjacent fingers of the signal gate, the carriers are bunched within the conducting wire, thus amplifying the current through the solid state Klystron at a frequency of the signal to the signal gate, thus achieving a power gain.
摘要翻译：通过在导线的两端形成源极接触和漏极接触并且在导线上形成偏置栅极和信号栅极来制造固态速调管结构。导线可以是至少一个碳纳米管或具有长的弹道平均自由路径的至少一个半导体线。通过以对应于信号栅极的相邻指状物之间的弹道载体的渡越时间的整数倍的频率施加信号，载流子在导线内聚束，从而以一定频率放大通过固态速调管的电流信号到信号门，从而实现功率增益。

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