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1. 发明授权

US09099327B2 Multigate structure formed with electroless metal deposition 有权
标题翻译：用无电金属沉积形成多孔结构
公开(公告)号：US09099327B2
公开(公告)日：2015-08-04
申请号：US13568839
申请日：2012-08-07
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/06 , H01L21/8238 , H01L29/417
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.
摘要翻译：一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

2. 发明申请

US20120298965A1 MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION 有权
标题翻译：具有电沉积金属沉积的多孔结构
公开(公告)号：US20120298965A1
公开(公告)日：2012-11-29
申请号：US13568839
申请日：2012-08-07
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/772 , B82Y99/00
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.
摘要翻译：一种多栅格结构，包括半导体衬底; 位于基板上的小于20纳米厚的超薄硅或碳体; 选择性地位于超薄硅或碳体的侧表面和顶表面上的无电沉积金属层，并且选择性地位于多结构结构的顶部上以与超薄硅或碳体电接触并最小化寄生电阻并且其中位于其上的超薄硅或碳体和金属层形成源区和漏区以及制造该结构的工艺。

3. 发明申请

US20120132989A1 MULTIGATE STRUCTURE FORMED WITH ELECTROLESS METAL DEPOSITION 有权
公开(公告)号：US20120132989A1
公开(公告)日：2012-05-31
申请号：US12955388
申请日：2010-11-29
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

4. 发明授权

US08936978B2 Multigate structure formed with electroless metal deposition 有权
公开(公告)号：US08936978B2
公开(公告)日：2015-01-20
申请号：US12955388
申请日：2010-11-29
申请人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
发明人： Wilfried Haensch , Christian Lavoie , Christine Qiqing Ouyang , Xiaoyan Shao , Paul M. Solomon , Zhen Zhang , Bin Yang
IPC分类号： H01L29/06 , H01L29/417
CPC分类号： H01L29/0673 , H01L21/823814 , H01L29/41791
摘要： A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

5. 发明授权

US08741753B2 Use of band edge gate metals as source drain contacts 有权
标题翻译：使用带边栅极金属作为源极漏极触点
公开(公告)号：US08741753B2
公开(公告)日：2014-06-03
申请号：US13611736
申请日：2012-09-12
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20 , H01L21/3205 , H01L21/00
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
摘要翻译：一种器件包括形成在半导体衬底中的沟道上方的栅叠层。栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。该装置还包括邻近通道的源极和漏极接触。源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

6. 发明申请

US20130241008A1 Use of Band Edge Gate Metals as Source Drain Contacts 有权
标题翻译：使用带边缘栅极金属作为源极漏极触点
公开(公告)号：US20130241008A1
公开(公告)日：2013-09-19
申请号：US13611736
申请日：2012-09-12
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A device includes a gate stack formed over a channel in a semiconductor substrate. The gate stack includes a layer of gate insulator material, a layer of gate metal overlying the layer of gate insulator material, and a layer of contact metal overlying the layer band edge gate metal. The device further includes source and drain contacts adjacent to the channel. The source and drain contacts each include a layer of the gate metal that overlies and is in direct electrical contact with a doped region of the semiconductor substrate, and a layer of contact metal that overlies the layer of gate metal.
摘要翻译：一种器件包括形成在半导体衬底中的沟道上方的栅叠层。栅极堆叠包括栅极绝缘体材料层，覆盖栅极绝缘体材料层的栅极金属层和覆盖层带边缘栅极金属的接触金属层。该装置还包括邻近通道的源极和漏极接触。源极和漏极触点各自包括覆盖并与半导体衬底的掺杂区域直接电接触的栅极金属层以及覆盖在栅极金属层上的接触金属层。

7. 发明申请

US20130241007A1 USE OF BAND EDGE GATE METALS AS SOURCE DRAIN CONTACTS 审中-公开
标题翻译：使用带边缘金属作为源漏联系
公开(公告)号：US20130241007A1
公开(公告)日：2013-09-19
申请号：US13421276
申请日：2012-03-15
申请人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
发明人： Kisik Choi , Christian Lavoie , Paul M. Solomon , Bin Yang , Zhen Zhang
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/7833 , H01L21/28512 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A method includes providing a semiconductor substrate having intentionally doped surface regions, the intentionally doped surface regions corresponding to locations of a source and a drain of a transistor; depositing a layer a band edge gate metal onto a gate insulator layer in a gate region of the transistor while simultaneously depositing the band edge gate metal onto the surface of the semiconductor substrate to be in contact with the intentionally doped surface regions; and depositing a layer of contact metal over the band edge gate metal in the gate region and in the locations of the source and the drain. The band edge gate metal in the source/drain regions reduces a Schottky barrier height of source/drain contacts of the transistor and serves to reduce contact resistance. A transistor fabricated in accordance with the method is also described.
摘要翻译：一种方法包括提供具有有意掺杂的表面区域的半导体衬底，有意掺杂的表面区域对应于晶体管的源极和漏极的位置; 在晶体管的栅极区域中的栅绝缘体层上沉积带边缘栅极金属层，同时将带边缘栅极金属沉积到半导体衬底的表面上以与有意掺杂的表面区域接触; 以及在所述栅极区域中以及所述源极和漏极的位置中的所述带边缘栅极金属之上沉积接触金属层。源极/漏极区域中的带边缘栅极金属降低了晶体管的源极/漏极接触的肖特基势垒高度，并且用于降低接触电阻。还描述了根据该方法制造的晶体管。

8. 发明授权

US08456011B2 Method to control metal semiconductor micro-structure 有权
公开(公告)号：US08456011B2
公开(公告)日：2013-06-04
申请号：US13006664
申请日：2011-01-14
申请人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
发明人： Christian Lavoie , Ahmet S. Ozcan , Zhen Zhang , Bin Yang
IPC分类号： H01L23/532
CPC分类号： H01L21/768 , H01L21/28518 , H01L23/485 , H01L29/456 , H01L29/66545 , H01L29/66575 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

9. 发明授权

US08278200B2 Metal-semiconductor intermixed regions 有权
标题翻译：金属半导体混合区域
公开(公告)号：US08278200B2
公开(公告)日：2012-10-02
申请号：US13012043
申请日：2011-01-24
申请人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
发明人： Christian Lavoie , Tak H. Ning , Ahmet S. Ozcan , Bin Yang , Zhen Zhang
IPC分类号： H01L21/20
CPC分类号： H01L21/28518
摘要： In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.
摘要翻译：在一个示例性实施例中，一种可由机器读取的程序存储设备，其有形地体现了可由机器执行的用于执行操作的指令程序，所述操作包括：在半导体结构的表面上沉积具有第一金属的第一层，第一层在第一层和半导体结构的界面处形成第一混合区; 去除沉积的第一层的一部分以暴露第一混合区; 在所述第一混合区域上沉积具有第二金属的第二层，其中沉积所述第二层在所述第二层和所述第一混合区的界面处产生第二混合区; 去除沉积的第二层的一部分以暴露第二混合区; 以及在所述半导体结构上执行至少一个退火。

10. 发明授权

US08168503B2 Method for forming an SOI schottky source/drain device to control encroachment and delamination of silicide 有权
标题翻译：用于形成SOI肖特基源极/漏极器件以控制硅化物侵蚀和分层的方法
公开(公告)号：US08168503B2
公开(公告)日：2012-05-01
申请号：US12726736
申请日：2010-03-18
申请人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
发明人： Marwan H. Khater , Christian Lavoie , Bin Yang , Zhen Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7839 , H01L29/78654
摘要： A method of fabricating a Schottky field effect transistor is provided that includes providing a substrate having at least a first semiconductor layer overlying a dielectric layer, wherein the first semiconductor layer has a thickness of less than 10.0 nm. A gate structure is formed directly on the first semiconductor layer. A raised semiconductor material is selectively formed on the first semiconductor layer adjacent to the gate structure. The raised semiconductor material is converted into Schottky source and drain regions composed of a metal semiconductor alloy. A non-reacted semiconductor material is present between the Schottky source and drain regions and the dielectric layer.
摘要翻译：提供一种制造肖特基场效应晶体管的方法，其包括提供具有覆盖在电介质层上的至少第一半导体层的衬底，其中第一半导体层具有小于10.0nm的厚度。栅极结构直接形成在第一半导体层上。凸起的半导体材料选择性地形成在与栅极结构相邻的第一半导体层上。凸起的半导体材料被转换成由金属半导体合金构成的肖特基源极和漏极区域。在肖特基源极和漏极区域与电介质层之间存在未反应的半导体材料。

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