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1. 发明授权

US5907485A Method and apparatus for flow control in packet-switched computer system 失效
标题翻译：分组交换计算机系统中流控制的方法和装置
公开(公告)号：US5907485A
公开(公告)日：1999-05-25
申请号：US414875
申请日：1995-03-31
申请人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
发明人： William C. Van Loo , Zahir Ebrahim , Satyanarayana Nishtala , Kevin B. Normoyle , Leslie Kohn , Louis F. Coffin, III
IPC分类号： G06F9/46 , G06F13/24 , G05B15/00
CPC分类号： G06F9/546 , G06F13/24
摘要： This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate. An acknowledgment from the downstream queue indicates to the sender that there is space in it for another transaction. Thus no system resources are wasted trying to send a request to a queue that is already full.
摘要翻译：本发明描述了一种用于分组交换单处理器和多处理器计算机系统的链路链路流控制方法，其使系统资源利用率和吞吐量最大化，并最小化系统等待时间。计算机系统包括一个或多个主接口，一个或多个从接口和互连系统控制器，其为每个主接口提供专用事务请求队列，并且控制事务到每个从接口的转发。主接口跟踪系统控制器中专用队列中的请求数，系统控制器跟踪每个从接口队列中的请求数。主接口和系统控制器都知道其下游队列的最大容量，并且不会比下游队列可以容纳更多的事务请求。来自下游队列的确认向发送方指示在其中存在另一个事务的空间。因此，尝试将请求发送到已满的队列时，不会浪费任何系统资源。

2. 发明授权

US5692197A Method and apparatus for reducing power consumption in a computer network without sacrificing performance 失效
标题翻译：用于在不牺牲性能的情况下降低计算机网络中的功耗的方法和装置
公开(公告)号：US5692197A
公开(公告)日：1997-11-25
申请号：US414879
申请日：1995-03-31
申请人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
发明人： Charles E. Narad , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Kevin B. Normoyle , Louis F. Coffin, III , Leslie Kohn
IPC分类号： G06F1/32 , G06F15/16 , G06F15/177
CPC分类号： G06F1/3209
摘要： A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independently initiating a transition into a power-conserving mode, i.e., a "sleep" state, while keeping its network interface "alive" and fully operational. Subsequently, each computer system can independently transition back into fully operational state, i.e., an "awake" state, when triggered by either a deterministic or an asynchronous event. As a result, the sleep states of the computer systems are transparent to the computer network. Deterministic events are events triggered internally by a computer system, e.g., an internal timer waking the computer system up at midnight to perform housekeeping chores such as daily tape backups. Conversely, the source of asynchronous events are external in nature and include input/output (I/O) activity. The illusion of the entire network being always fully operational is possible because the system controllers, the interconnects and network interfaces of each computer system remain fully operational while selected modules and peripheral devices are powered down. As a result, each computer system is able to rapidly awake from sleep state in response to stimuli by powering down selected modules thereby accomplishing power conservation without requiring a static shut down of the computer network, i.e., without the overall performance and response of the computer network.
摘要翻译：一种用于主动管理计算机网络的整体功耗的方法和装置，其包括彼此互连的多个计算机系统。反过来，每个计算机系统具有一个或多个模块。计算机网络的每个计算机系统能够独立地启动向省电模式转变，即“休眠”状态，同时保持其网络接口“活着”并且完全可操作。随后，当由确定性或异步事件触发时，每个计算机系统可以独立地转换回完全操作状态，即“清醒”状态。因此，计算机系统的睡眠状态对于计算机网络是透明的。确定性事件是由计算机系统在内部触发的事件，例如内部定时器在午夜唤醒计算机系统以执行诸如日常磁带备份的家务杂务。相反，异步事件的来源本质上是外部的，包括输入/输出（I / O）活动。整个网络的错觉始终是完全可操作的，因为每个计算机系统的系统控制器，互连和网络接口在选定的模块和外围设备关闭电源时保持完全可操作。因此，每个计算机系统能够通过断电所选择的模块来迅速地从睡眠状态唤醒，从而实现功率节省，而不需要静态关闭计算机网络，即没有计算机的整体性能和响应网络。

3. 发明授权

US5862356A Pipelined distributed bus arbitration system 失效
标题翻译：流水线分布式总线仲裁系统
公开(公告)号：US5862356A
公开(公告)日：1999-01-19
申请号：US870438
申请日：1997-06-04
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
IPC分类号： G06F15/16 , G06F13/368 , G06F13/374 , G06F15/177 , G06F13/00
CPC分类号： G06F13/368 , G06F13/374
摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration occurs within all the respective bus arbiters occurs in a second clock cycle.
摘要翻译：本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求仲裁时钟周期。此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器内进行仲裁发生在第二个时钟周期。

4. 发明授权

US5710891A Pipelined distributed bus arbitration system 失效
标题翻译：流水线分布式总线仲裁系统
公开(公告)号：US5710891A
公开(公告)日：1998-01-20
申请号：US414559
申请日：1995-03-31
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Louis F. Coffin, III
IPC分类号： G06F15/16 , G06F13/368 , G06F13/374 , G06F15/177 , G06F13/00
CPC分类号： G06F13/368 , G06F13/374
摘要： The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e., the bus master driving the system bus, preferentially. Each arbitration task is completed within a system clock cycle regardless of processor speed. As a result, the arbitration latency for retaining the current bus master is one system clock cycle while the latency for selecting and switching bus masters is two system clock cycles. In this implementation, a last port driver is the only sub-system permitted to assert a bus request in a clock cycle and immediately drive the system bus in the next immediate clock cycle. Conversely, when a second sub-system which is not the last port driver needs to drive an inactive system bus, the second sub-system asserts its bus request line in a first clock cycle, and arbitration within all the respective bus arbiters occurs in a second clock cycle.
摘要翻译：本发明提供了一种可扩展的，模块化和流水线分布式总线仲裁系统，用于有效地分辨耦合到公共系统总线的子系统（例如处理器）之间的总线争用。仲裁系统包括多个分布式总线仲裁器，其接收来自子系统的总线请求并独立地确定下一个总线主机。仲裁协议使仲裁过程能够从临界定时路径中消除，从而允许系统以给定的集成电路（IC）技术可能的最大系统时钟频率工作，以减少整体系统时钟延迟。在仲裁时钟周期期间，子系统之间的任何改变都是基于任何在仲裁时钟周期之前的时钟周期期间有效的系统总线请求，并且独立于在系统总线请求期间断言的任何系统总线请求仲裁时钟周期。此外，仲裁协议优先处理当前总线主机，即总线主机驱动系统总线。无论处理器速度如何，每个仲裁任务都在系统时钟周期内完成。因此，用于保留当前总线主机的仲裁延迟是一个系统时钟周期，而用于选择和切换总线主机的延迟是两个系统时钟周期。在此实现中，最后一个端口驱动程序是允许在时钟周期内断言总线请求的唯一子系统，并在下一个即时时钟周期内立即驱动系统总线。相反，当不是最后端口驱动器的第二子系统需要驱动非活动系统总线时，第二子系统在第一时钟周期内断言其总线请求线，并且在所有相应的总线仲裁器中进行仲裁发生在第二个时钟周期。

5. 发明授权

US5892957A Method and apparatus for interrupt communication in packet-switched microprocessor-based computer system 失效
标题翻译：用于基于分组交换微处理器的计算机系统中的中断通信的方法和装置
公开(公告)号：US5892957A
公开(公告)日：1999-04-06
申请号：US868171
申请日：1997-06-03
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

6. 发明授权

US5689713A Method and apparatus for interrupt communication in a packet-switched computer system 失效
标题翻译：分组交换计算机系统中的中断通信的方法和装置
公开(公告)号：US5689713A
公开(公告)日：1997-11-18
申请号：US425537
申请日：1995-04-20
申请人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
发明人： Kevin B. Normoyle , Zahir Ebrahim , Satyanarayana Nishtala , William C. Van Loo , Sun-Den Chen , Charles E. Narad
IPC分类号： G06F15/173 , G06F9/46 , G06F9/48 , G06F13/24 , G06F13/14
CPC分类号： G06F9/546 , G06F13/24
摘要： An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers. When an interrupt request is sent from an interrupter, the system controller determines a target for the request, which may be by a target ID in the request or may be based upon a predetermined method to ensure even distribution of interrupt requests among all or a subset of the interrupt handlers. The system controller determines whether the target interrupt handler's input queue is full, and if not then it passes on the interrupt request and sends a positive acknowledgment to the interrupter. If the queue is full, then a negative acknowledgment is sent, and the interrupter then waits a random period of time and sends the interrupt request again. The target interrupt handler may thus accept multiple interrupt requests and process them in order without negative acknowledgments.
摘要翻译：一种用于处理从多个中断器中的任一个到多个中断处理程序中的任何一个的中断请求的装置和方法。每个中断处理程序包括用于保持多个输入中断请求的中断输入请求队列。系统控制器连接到断续器和中断处理器，并且包括耦合到每个中断器的输入队列，用于接收多个中断请求。系统控制器包括处理器和存储用于控制其操作的指令的存储器。系统控制器还包括耦合到每个中断处理器（在许多情况下也将是中断器）的输出队列，以及用于在任何给定时间监视每个中断输入队列中的中断请求的当前号码的计数器中断处理程序。当从中断器发送中断请求时，系统控制器确定请求的目标，该请求可以是请求中的目标ID，或者可以基于预定的方法来确保所有或一个子集中的中断请求的均匀分配的中断处理程序。系统控制器确定目标中断处理程序的输入队列是否已满，如果不是，则它传递中断请求并向中断器发送肯定确认。如果队列已满，则发送否定确认，然后中断器等待随机时间段，并再次发送中断请求。因此，目标中断处理程序可以接受多个中断请求并按顺序进行处理，而不会产生否定的确认。

7. 发明申请

US20080235558A1 Subsystem and Method for Encoding 64-bit Data Nibble Error Correct and Cyclic-Redundancy Code (CRC) Address Error Detect for Use in a 76-bit Memory Module 有权
标题翻译：用于编码64位数据半字节错误正确和循环冗余码（CRC）的子系统和方法用于76位内存模块的地址错误检测
公开(公告)号：US20080235558A1
公开(公告)日：2008-09-25
申请号：US12132839
申请日：2008-06-04
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

8. 发明授权

US07398449B1 Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module 有权
标题翻译：编码64位数据半字节错误纠错和循环冗余码（CRC）地址错误检测用于76位内存模块
公开(公告)号：US07398449B1
公开(公告)日：2008-07-08
申请号：US11161042
申请日：2005-07-20
申请人： Kevin B. Normoyle , Robert G. Hathaway
发明人： Kevin B. Normoyle , Robert G. Hathaway
IPC分类号： H03M13/00
CPC分类号： G06F11/1016 , G11C5/04 , G11C7/1006 , G11C2029/0409
摘要： A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs.
摘要翻译：存储器系统提供数据错误检测和校正以及地址错误检测。循环冗余校验（CRC）代码生成地址校验位。使用CRC代码将32位地址压缩为6个地址校验位。 6个地址校验位连接64个数据位和2个标志位，以产生72位校验字。 72位检查字被输入到纠错码（ECC）发生器中，该纠错码产生12个校验位，存储在64位数据位的存储器中。 76位存储器模块可以存储64个数据和12个校验位。可以纠正半字节错误，并且可以检测到所有的半字节+ 1位错误。此外，可以检测位序列中的6位错误。这允许检测地址的6位CRC中的所有错误。 CRC码和ECC是检测复用地址DRAM共同的双位错误的理想选择。

9. 发明授权

US5070475A Floating point unit interface 失效
标题翻译：浮点单元接口
公开(公告)号：US5070475A
公开(公告)日：1991-12-03
申请号：US797856
申请日：1985-11-14
申请人： Kevin B. Normoyle , James M. Guyer , Rainer Vogt , Anthony S. Fong
发明人： Kevin B. Normoyle , James M. Guyer , Rainer Vogt , Anthony S. Fong
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.
摘要翻译：一种数据处理系统，包括与中央处理单元（CPU）连接的浮点计算单元（FPU），其中CPU提供调度控制信号以通知FPU它即将执行浮点宏指令，并提供调度地址，其在提供调度控制信号的相同操作周期期间包括其浮点微指令的起始地址。在FPU中提供缓冲存储器以存储一个解码的宏指令的起始地址，而FPU正在执行先前解码的宏指令的微指令序列。当缓冲区已经存在驻留在其缓冲器中的起始地址时，FPU提供控制信号，以防止CPU提供进一步的调度地址，直到缓冲区为空。还提供了用于同步CPU和FPU操作和数据传输的其他控制信号。

10. 发明授权

US5987081A Method and apparatus for a testable high frequency synchronizer 失效
标题翻译：用于可测试的高频同步器的方法和装置
公开(公告)号：US5987081A
公开(公告)日：1999-11-16
申请号：US884253
申请日：1997-06-27
申请人： Michael A. Csoppenszky , Kevin B. Normoyle , Prakash Narain
发明人： Michael A. Csoppenszky , Kevin B. Normoyle , Prakash Narain
IPC分类号： G06F5/06 , H04L7/00 , H04L7/02
CPC分类号： G06F5/06 , H04L7/0012 , H04L7/02 , H04L7/0004
摘要： A synchronizer comprised in part of a series of flip-flops is used to deterministically transfer data between clock domains during system test. Flip-flops in the clock domain operating at a higher clock frequency have a clock enable signal. The clock enable signal is defined so as to approximately align the enabled rising clock edges of the faster clock signal with the falling edges of the slower clock signal. This approximate alignment provides a timing window of one half period of the slower clock for the data to stabilize at the input of a flip-flop in the faster clock domain before it is sampled. This ensures deterministic transfer of data. Data flow control circuitry can be used to provide a ready signal to the faster clock domain to indicate that the synchronizer is available to transfer a synchronization signal. After testing is complete, the synchronizer can operate in an application mode wherein one or more of the clock enable signals is set to a continuous high level to minimize latency.
摘要翻译：在系统测试期间，使用包括在一系列触发器中的同步器来确定性地在时钟域之间传送数据。在较高时钟频率下操作的时钟域中的触发器具有时钟使能信号。时钟使能信号被定义为使得较快时钟信号的使能的上升时钟沿与较慢时钟信号的下降沿近似对准。这种近似对准提供了较慢时钟的一个半周期的定时窗口，以便数据在采样之前在更快的时钟域中稳定在触发器的输入端。这确保数据的确定性传输。数据流控制电路可用于向较快的时钟域提供就绪信号，以指示同步器可用于传送同步信号。测试完成后，同步器可以以应用模式工作，其中一个或多个时钟使能信号被设置为连续的高电平以最小化等待时间。

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