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1. 发明授权

US07266675B2 Processor including a register file and method for computing flush masks in a multi-threaded processing system 有权
标题翻译：处理器包括用于在多线程处理系统中计算闪存掩码的寄存器文件和方法
公开(公告)号：US07266675B2
公开(公告)日：2007-09-04
申请号：US11324399
申请日：2006-01-03
申请人： William Elton Burky , Peter Juergen Klim
发明人： William Elton Burky , Peter Juergen Klim
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the column having an index equal to the row selector is automatically reset (excepting the absent cell mentioned above) . On a read of a row, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.
摘要翻译：包括用于在多线程处理系统中计算闪存掩码的寄存器文件和方法的处理器响应于多个刷新请求源而提供刷新结果的快速和低逻辑开销计算。刷新掩码寄存器文件由数组中的多个单元格实现，其中单元格不在对角线，其中列索引等于行索引。每个单元都具有垂直写入使能和水平写入使能。当写入一行以验证该行的标签值时，具有等于行选择器的索引的列将自动重置（除了上述缺少的单元格）。在读取一行时，每列提供的有线AND电路提供了与上一次重置行之后写入的其他行相对应的位字段，该行是指示较新标签和所选标签的刷新掩码。

2. 发明授权

US07015718B2 Register file apparatus and method for computing flush masks in a multi-threaded processing system 失效
标题翻译：用于在多线程处理系统中计算闪存掩码的注册文件装置和方法
公开(公告)号：US07015718B2
公开(公告)日：2006-03-21
申请号：US10422684
申请日：2003-04-21
申请人： William Elton Burky , Peter Juergen Klim
发明人： William Elton Burky , Peter Juergen Klim
IPC分类号： H03K19/177
CPC分类号： G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： A method and apparatus for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the is column having an index equal to the row selector is automatically reset (excepting the bit corresponding to the absent cell mentioned above). On a read of a row in the array, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag. Each cell in the array has an output for each thread supported by the array, and the logic provides a flush mask output for each thread as well as a combined flush mask output that supports simultaneous access for all of the threads.
摘要翻译：用于在多线程处理系统中计算闪存掩码的方法和装置响应于多个刷新请求源而提供刷新结果的快速和低逻辑开销计算。刷新掩码寄存器文件由数组中的多个单元格实现，其中单元格不在对角线，其中列索引等于行索引。每个单元都具有垂直写入使能和水平写入使能。当一行被写入以验证该行的标签值时，具有等于行选择器的索引的列被自动复位（除了与上述缺少的单元格相对应的位）。在阵列中的一行读取中，每列提供的有线AND电路提供了与自行的最后一次复位以来写入的其他行相对应的位字段，该行是指示较新标记的刷新掩码，并且所选择的标签。数组中的每个单元格都具有数组支持的每个线程的输出，逻辑为每个线程提供了一个刷新掩码输出以及一个组合的刷新输出，支持所有线程的同时访问。

3. 发明授权

US07506230B2 Transient noise detection scheme and apparatus 有权
标题翻译：瞬态噪声检测方案和装置
公开(公告)号：US07506230B2
公开(公告)日：2009-03-17
申请号：US11050351
申请日：2005-02-03
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： G01R31/28
CPC分类号： G06F11/24
摘要： A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.
摘要翻译：一种用于检测非数据流电路中的软错误的方法，系统和装置。在优选实施例中，在锁存系统处接收输入。闩锁系统由两对闩锁组成。第二对闩锁平行于第一对闩锁。两对锁存器捕获输入。然而，第二对锁存器相对于第一对锁存器锁存器在时间上稍后捕获输入。捕获的输入然后从每对闩锁中的第一锁存器传送到每对锁存器中的第二锁存器。比较两个第二个锁存器中的输入。如果在两个第二锁存器中捕获的输入不相同，则将信息发送到恢复单元。

4. 发明授权

US07202704B2 Leakage sensing and keeper circuit for proper operation of a dynamic circuit 失效
标题翻译：泄漏检测和保持电路用于动态电路的正常运行
公开(公告)号：US07202704B2
公开(公告)日：2007-04-10
申请号：US10937703
申请日：2004-09-09
申请人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
发明人： Sam Gat-Shang Chu , Peter Juergen Klim , Michael Ju Hyeok Lee , Jose Angel Paredes
IPC分类号： H03K19/096 , H03K19/00 , H03K19/20 , H03K19/094 , G01R31/02
CPC分类号： H03K19/0963
摘要： A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is connected with a respective one of a plurality of keeper circuits that reside at the dynamic circuit. Each of the plurality of keeper circuits has a unique size ratio with respect to a logic element size of the dynamic circuit.
摘要翻译：提供一种用于确保动态电路的正确操作的方法和装置。动态电路实例具有连接到多个泄漏检测器电路中的相应一个的多个输出。每个泄漏检测器电路的输出与位于动态电路的多个保持器电路中的相应一个连接。多个保持器电路中的每一个相对于动态电路的逻辑元件尺寸具有独特的尺寸比。

5. 发明授权

US06785826B1 Self power audit and control circuitry for microprocessor functional units 失效
标题翻译：用于微处理器功能单元的自检审计和控制电路
公开(公告)号：US06785826B1
公开(公告)日：2004-08-31
申请号：US08682471
申请日：1996-07-17
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A method and apparatus for reducing power dissipation within a functional unit of a microprocessor includes a power sensing circuit for sensing power dissipation of the functional unit. A low power mode identifying circuit identifies when the measured power dissipation of the functional unit exceeds a predetermined amount or value. Upon such a condition, a low power mode circuit operates the functional unit in a low power mode thereby reducing its power dissipation. Operation of the functional unit in the low power mode continues until the power dissipation reaches a safe level. The functional unit internally determines power dissipation and selectively enters a low power mode to reduce power dissipation of the functional unit. Low power mode operation of the functional unit reduces power dissipation of the functional unit.
摘要翻译：一种用于降低微处理器的功能单元内功耗的方法和装置，包括用于感测功能单元的功耗的功率检测电路。低功率模式识别电路识别功能单元的测量功耗何时超过预定量或值。在这种情况下，低功率模式电路以低功率模式操作功能单元，从而降低其功耗。低功耗模式下的功能单元的运行持续到功耗达到安全水平。功能单元内部确定功耗，并选择性地进入低功耗模式以降低功能单元的功耗。功能单元的低功耗模式操作降低了功能单元的功耗。

6. 发明授权

US06522170B1 Self-timed CMOS static logic circuit 失效
标题翻译：自定时CMOS静态逻辑电路
公开(公告)号：US06522170B1
公开(公告)日：2003-02-18
申请号：US09067153
申请日：1998-04-27
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： H03K1900
CPC分类号： H03K19/0966
摘要： A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.
摘要翻译：已经发明了一种自定时CMOS静态电路技术，其提供了对源电路的完全握手; 通过互锁内部和外部信号来防止输入数据丢失; 电路和接收器之间完全握手自定时电路; 借助于输出数据信息的内部锁定来防止丢失的访问操作信息; 以及一些类型的动态自定时系统的插件兼容性。整个系统的最终结果是现在可以使用静态CMOS电路来生成自定时系统。这与依赖于动态电路的现有自定时系统形成对比。因此，可以保持静态电路的质量并充分利用它们。

7. 发明授权

US06285217B1 Dynamic logic circuits with reduced evaluation time 失效
标题翻译：动态逻辑电路减少评估时间
公开(公告)号：US06285217B1
公开(公告)日：2001-09-04
申请号：US09391423
申请日：1999-09-08
申请人： Christopher McCall Durham , Peter Juergen Klim , Younes Lofti , John Beck
发明人： Christopher McCall Durham , Peter Juergen Klim , Younes Lofti , John Beck
IPC分类号： H03K19096
CPC分类号： G11C7/065
摘要： Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.
摘要翻译：具有减少评估时间的动态逻辑电路通过提高逻辑输入梯级的连接点处的电压变化率，在动态评估逻辑电路方面提供更快的输出。一旦节点开始评估，这些电路使用交叉耦合放大器对输入梯形图组合节点进行充电。

8. 发明授权

US6115789A Method and system for determining which memory locations have been accessed in a self timed cache architecture 失效
标题翻译：用于确定在自定时高速缓存结构中已经访问了哪些存储器位置的方法和系统
公开(公告)号：US6115789A
公开(公告)日：2000-09-05
申请号：US845868
申请日：1997-04-28
申请人： Christopher McCall Durham , Hieu Trong Ngo , Peter Juergen Klim
发明人： Christopher McCall Durham , Hieu Trong Ngo , Peter Juergen Klim
IPC分类号： G11C29/32 , G06F12/00 , G11C29/00
CPC分类号： G11C29/32
摘要： The present invention provides a method and system for providing observability of memory address access for self-timed cache designs. A system according to the present invention for determining which memory location has been accessed in a self-timed cache comprises a content addressable memory; a secondary memory coupled to the content addressable memory, wherein the secondary memory includes at least one memory location which may be selected by the content addressable memory based upon a self-timed cache access. The system further includes a test circuitry coupled to the content addressable memory, wherein the test circuitry stores a pointer which points to a selected memory location in response to the self-timed cache access of the secondary memory.
摘要翻译：本发明提供了一种用于提供用于自定时高速缓存设计的存储器地址访问的可观察性的方法和系统。根据本发明的用于确定在自定时高速缓存中已经访问了哪个存储器位置的系统包括内容可寻址存储器; 耦合到内容可寻址存储器的辅助存储器，其中辅存储器包括可以由内容可寻址存储器基于自定时高速缓存访问来选择的至少一个存储器位置。系统还包括耦合到内容可寻址存储器的测试电路，其中测试电路响应于辅助存储器的自定时高速缓存访问而存储指向所选存储器位置的指针。

9. 发明授权

US5790560A Apparatus and method for timing self-timed circuitry 失效
标题翻译：定时自定时电路的装置和方法
公开(公告)号：US5790560A
公开(公告)日：1998-08-04
申请号：US767247
申请日：1996-12-13
申请人： Christopher McCall Durham , Peter Juergen Klim
发明人： Christopher McCall Durham , Peter Juergen Klim
IPC分类号： G01R31/28 , G01R31/30 , G01R31/3193
CPC分类号： G01R31/30 , G01R31/2882 , G01R31/31937
摘要： A method and apparatus for timing self-timed circuitry measures the cycle time of a self-timed system or circuit. An input pattern generator generates a plurality of data input patterns that are sequentially input to the self-timed system or circuit. A valid output signal, generated after the self-timed system or circuit produces output signal(s) in response to each data input pattern and signals the input pattern generator to change the input to the next data input pattern. A timer measures the total amount of time required for the self-timed system or circuit to generate output signal(s) in response to the sequential input of each of the data input patterns. A counter counts the number of times a valid output signal is generated as the apparatus loops through each of the data input patterns. The timer result is divided by the counter result to determine the average cycle time (time delay) of a self-timed system or circuit across multiple data input patterns.
摘要翻译：用于定时自定时电路的方法和装置测量自定时系统或电路的周期时间。输入图案生成器生成顺序地输入到自定时系统或电路的多个数据输入模式。在自定时系统或电路之后产生的有效输出信号响应于每个数据输入模式产生输出信号，并且向输入模式发生器发信号，以将输入改变为下一个数据输入模式。定时器测量自适应系统或电路响应于每个数据输入模式的顺序输入而产生输出信号所需的总时间量。当计数器循环通过每个数据输入模式时，计数器计数生成有效输出信号的次数。定时器结果除以计数器结果，以确定跨多个数据输入模式的自定时系统或电路的平均周期时间（时间延迟）。

10. 发明授权

US07173882B2 Methods and systems for performing horological functions using time cells 有权
标题翻译：使用时间单元执行钟表功能的方法和系统
公开(公告)号：US07173882B2
公开(公告)日：2007-02-06
申请号：US11059279
申请日：2005-02-15
申请人： Viktors Berstis , Peter Juergen Klim , Chung Lam
发明人： Viktors Berstis , Peter Juergen Klim , Chung Lam
IPC分类号： G04F8/00 , G04F10/00 , G01R31/26 , H01L25/00
CPC分类号： H01L27/115 , G04F1/005 , G04F10/10 , G06Q30/0207
摘要： A simple electronic horological device, termed a time cell, is presented with associated methods, systems, and computer program products. A time cell has an insulated, charge storage element that receives an electrostatic charge through its insulating medium, i.e. it is programmed. Over time, the charge storage element then loses the electrostatic charge through its insulating medium. Given the reduction of the electric potential of the programmed charge storage element at a substantially known discharge rate, and by observing the electric potential of the programmed charge storage element at a given point in time, an elapsed time period can be determined. Thus, the time cell is able to measure an elapsed time period without a continuous power source.
摘要翻译：被称为时间单元的简单的电子钟表装置被提供有相关的方法，系统和计算机程序产品。时间单元具有绝缘的电荷存储元件，其通过其绝缘介质接收静电电荷，即它被编程。随着时间的推移，电荷存储元件然后通过其绝缘介质失去静电荷。考虑到以基本上已知的放电速率降低编程电荷存储元件的电位，并且通过在给定时间点观察编程电荷存储元件的电位，可以确定经过时间。因此，时间单元能够测量经过的时间段而没有连续的电源。

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