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1. 发明授权

US09043586B2 Memory training results corresponding to a plurality of memory modules 有权
标题翻译：对应于多个存储器模块的存储器训练结果
公开(公告)号：US09043586B2
公开(公告)日：2015-05-26
申请号：US13332092
申请日：2011-12-20
申请人： William H. Cox, Jr. , Jimmy G. Foster, Sr. , Sumeet Kochar , Ivan R. Zapata
发明人： William H. Cox, Jr. , Jimmy G. Foster, Sr. , Sumeet Kochar , Ivan R. Zapata
IPC分类号： G06F9/00 , G06F13/00 , G06F12/06
CPC分类号： G06F12/0646 , G06F11/3051 , G11C5/04 , G11C7/1066 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.
摘要翻译：提供了用于改善对应于多个存储器模块的存储器训练结果的方法，装置和计算机程序产品。实施例包括在启动包括多个存储器模块的系统的引导顺序时检测硬件配置变化; 产生多个训练迭代，对应于数据选通（DQS）信号与所述多个存储器模块的数据有效数据（DQ）行窗口的对准的参考训练值; 识别每个训练迭代，为该训练迭代生成的参考训练值内的任何外部值; 从参考训练值中消除所识别的外部值; 基于剩余参考训练值的平均值生成最终参考训练值; 并使用最终参考训练值作为系统引导顺序的DQ-DQS定时值。

2. 发明申请

US20130159687A1 Memory Training Results Corresponding To A Plurality Of Memory Modules 有权
标题翻译：内存培训结果对应于多个内存模块
公开(公告)号：US20130159687A1
公开(公告)日：2013-06-20
申请号：US13332092
申请日：2011-12-20
申请人： William H. Cox, JR. , Jimmy G. Foster, SR. , Sumeet Kochar , Ivan R. Zapata
发明人： William H. Cox, JR. , Jimmy G. Foster, SR. , Sumeet Kochar , Ivan R. Zapata
IPC分类号： G06F15/177
CPC分类号： G06F12/0646 , G06F11/3051 , G11C5/04 , G11C7/1066 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.
摘要翻译：提供了用于改善对应于多个存储器模块的存储器训练结果的方法，装置和计算机程序产品。实施例包括在启动包括多个存储器模块的系统的引导顺序时检测硬件配置变化; 产生多个训练迭代，对应于数据选通（DQS）信号与所述多个存储器模块的数据有效数据（DQ）行窗口的对准的参考训练值; 识别每个训练迭代，为该训练迭代生成的参考训练值内的任何外部值; 从参考训练值中消除所识别的外部值; 基于剩余参考训练值的平均值生成最终参考训练值; 并使用最终参考训练值作为系统引导顺序的DQ-DQS定时值。

3. 发明授权

US08429441B2 Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor 失效
标题翻译：通过发送高于实际电流量信号进行监控，操作处理器低于最大涡轮模式频率
公开(公告)号：US08429441B2
公开(公告)日：2013-04-23
申请号：US12762419
申请日：2010-04-19
申请人： Brian A. Baker , Justin P. Bandholz , William H. Cox, Jr. , Sumeet Kochar , Ivan R. Zapata
发明人： Brian A. Baker , Justin P. Bandholz , William H. Cox, Jr. , Sumeet Kochar , Ivan R. Zapata
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed.
摘要翻译：一种用于在涡轮增压状态下控制处理器的最大涡轮模式的方法，计算机程序产品和系统。该方法包括通过将由处理器提取的电流量过度报告给处理器的当前监视反馈线来限制处理器可用的最大涡轮模式，其中处理器使用过度报告的电流来维持处理器的操作处理器的性能规格。可以使用自动校准程序来确定可用于防止处理器性能超过最大涡轮模式的当前过度报告的标称量。在一个实施例中，数字电位计被包括在电压调节器电路中以按指示过度报告电流。

4. 发明申请

US20110258477A1 SELECTIVE LIMITS ON PROCESSOR TURBO MODES 失效
标题翻译：处理器涡轮模式的选择性限制
公开(公告)号：US20110258477A1
公开(公告)日：2011-10-20
申请号：US12762419
申请日：2010-04-19
申请人： Brian A. Baker , Justin P. Bandholz , William H. Cox, JR. , Sumeet Kochar , Ivan R. Zapata
发明人： Brian A. Baker , Justin P. Bandholz , William H. Cox, JR. , Sumeet Kochar , Ivan R. Zapata
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the processor by over-reporting the amount of current drawn by the processor to the current monitoring feedback line to the processor, wherein the processor uses the over-reported current to maintain operation of the processor within performance specifications of the processor. An automatic calibration routine may be used to determine nominal amounts of current over-reporting that may be used to prevent the processor performance from exceeding the maximum turbo mode. In one embodiment, a digital potentiometer is included in the voltage regulator circuit to over-report the current as instructed.
摘要翻译：一种用于在涡轮增压状态下控制处理器的最大涡轮模式的方法，计算机程序产品和系统。该方法包括通过将由处理器提取的电流量过度报告给处理器的当前监视反馈线来限制处理器可用的最大涡轮模式，其中处理器使用过度报告的电流来维持处理器的操作处理器的性能规格。可以使用自动校准程序来确定可用于防止处理器性能超过最大涡轮模式的当前过度报告的标称量。在一个实施例中，数字电位计被包括在电压调节器电路中以按指示过度报告电流。

5. 发明授权

US08102651B2 Airflow barriers for efficient cooling of memory modules 有权
标题翻译：用于高效冷却内存模块的气流屏障
公开(公告)号：US08102651B2
公开(公告)日：2012-01-24
申请号：US12572301
申请日：2009-10-02
申请人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, Sr. , Ivan R. Zapata
发明人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, Sr. , Ivan R. Zapata
IPC分类号： H05K7/20
CPC分类号： G06F1/20
摘要： Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.
摘要翻译：提供通过包括存储器模块的上游列和存储器模块的下游列的底盘的气流的方法和装置。气流被分为从上游塔的上游端延伸到下游塔的下游端的第一和第二分开的气流。第一气流引导与可操作地安装在上游塔中的单个存储器模块接触，并且避免与下游塔中的任何存储器模块接触。引导第二气流流以避免与上游塔中的任何存储器模块接触并与可操作地安装在下游塔中的单个存储器模块接触。即使在这样的存储器模块上的热负载较大，改进的冷却也能够每通道扩展使用单个存储器模块。结果是总体上节省了电力，因为冷却要求不再要求每个通道安装额外的内存模块，以便共享和分配热负载。

6. 发明申请

US20110080700A1 Airflow Barriers for Efficient Cooling of Memory Modules 有权
标题翻译：用于高效冷却内存模块的气流障碍
公开(公告)号：US20110080700A1
公开(公告)日：2011-04-07
申请号：US12572301
申请日：2009-10-02
申请人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, SR. , Ivan R. Zapata
发明人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, SR. , Ivan R. Zapata
IPC分类号： G06F1/20
CPC分类号： G06F1/20
摘要： Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.
摘要翻译：提供通过包括存储器模块的上游列和存储器模块的下游列的底盘的气流的方法和装置。气流被分为从上游塔的上游端延伸到下游塔的下游端的第一和第二分开的气流。第一气流引导与可操作地安装在上游塔中的单个存储器模块接触，并且避免与下游塔中的任何存储器模块接触。引导第二气流流以避免与上游塔中的任何存储器模块接触并与可操作地安装在下游塔中的单个存储器模块接触。即使在这样的存储器模块上的热负载较大，改进的冷却也能够每通道扩展使用单个存储器模块。结果是总体上节省了电力，因为冷却要求不再要求每个通道安装额外的内存模块，以便共享和分配热负载。

7. 发明申请

US20130117493A1 Reliable Memory Mapping In A Computing System 审中-公开
标题翻译：计算系统中可靠的内存映射
公开(公告)号：US20130117493A1
公开(公告)日：2013-05-09
申请号：US13289311
申请日：2011-11-04
申请人： Nathan C. Skalsky , Ivan R. Zapata
发明人： Nathan C. Skalsky , Ivan R. Zapata
IPC分类号： G06F12/06
CPC分类号： G06F12/0646
摘要： Methods, apparatus, and products for reliable memory mapping in a computing system, the computing system including a plurality of memory modules, including: determining, by a channel mapping module, a reliability rating for each of a plurality of memory controller address ranges; mapping, by the channel mapping module, critical system-level memory addresses to the most reliable memory controller address ranges; and directing, by the channel mapping module, memory accesses addressed to a critical system-level memory address to the most reliable memory controller address ranges.
摘要翻译：用于在计算系统中可靠存储器映射的方法，装置和产品，所述计算系统包括多个存储器模块，所述计算系统包括：由信道映射模块确定多个存储器控制器地址范围中的每一个的可靠性等级; 通过映射模块将关键系统级内存地址映射到最可靠的存储器控制器地址范围; 并且通过信道映射模块将寻址到关键系统级存储器地址的存储器访问引导到最可靠的存储器控制器地址范围。

8. 发明申请

US20130058037A1 Presence Detectable Baffle For Electrical Components In A Computing System 有权
公开(公告)号：US20130058037A1
公开(公告)日：2013-03-07
申请号：US13534255
申请日：2012-06-27
申请人： Mark A. Brandyberry , Todd W. Justus , Paul D. Kangas , Brent W. Yardley , Ivan R. Zapata
发明人： Mark A. Brandyberry , Todd W. Justus , Paul D. Kangas , Brent W. Yardley , Ivan R. Zapata
IPC分类号： G06F1/20
CPC分类号： H05K7/20145 , G06F1/20 , Y10T137/0318
摘要： A presence detectable baffle for electrical components in a computing system, including: a passive chassis having a form factor is consistent with an electrical component of the computing system; and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component.

9. 发明授权

US08495269B2 Administering computing system resources in a computing system 有权
标题翻译：管理计算系统中的计算系统资源
公开(公告)号：US08495269B2
公开(公告)日：2013-07-23
申请号：US13529217
申请日：2012-06-21
申请人： Mark A. Brandyberry , Todd W. Justus , Paul D. Kangas , Brent W. Yardley , Ivan R. Zapata
发明人： Mark A. Brandyberry , Todd W. Justus , Paul D. Kangas , Brent W. Yardley , Ivan R. Zapata
IPC分类号： G06F9/02 , H05K7/20
CPC分类号： G06F1/20 , G06F1/185
摘要： Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.
摘要翻译：在计算系统中管理计算系统资源，所述计算系统包括适于接收具有一组引脚的电气部件的至少一个插槽，所述插槽被配置为将安装在所述插槽内的所述电气部件的引脚耦合到所述计算系统存在可检测的挡板包括具有与电气部件一致的形状因数的无源底板和连接到被动底盘的存在可检测引脚组，该引脚与电部件一致，包括：由系统管理器识别，存在可检测的挡板; 并且由系统管理员根据存在的可检测的挡板属性来管理计算系统的操作属性。

10. 发明申请

US20130060983A1 Administering Computing System Resources In A Computing System 有权
公开(公告)号：US20130060983A1
公开(公告)日：2013-03-07
申请号：US13529217
申请日：2012-06-21
申请人： Mark A. Brandyberry , Todd W. Justus , Paul D. Kangas , Brent W. Yardley , Ivan R. Zapata
发明人： Mark A. Brandyberry , Todd W. Justus , Paul D. Kangas , Brent W. Yardley , Ivan R. Zapata
IPC分类号： G06F13/14
CPC分类号： G06F1/20 , G06F1/185
摘要： Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes.

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