专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09043586B2 Memory training results corresponding to a plurality of memory modules 有权
标题翻译：对应于多个存储器模块的存储器训练结果
公开(公告)号：US09043586B2
公开(公告)日：2015-05-26
申请号：US13332092
申请日：2011-12-20
申请人： William H. Cox, Jr. , Jimmy G. Foster, Sr. , Sumeet Kochar , Ivan R. Zapata
发明人： William H. Cox, Jr. , Jimmy G. Foster, Sr. , Sumeet Kochar , Ivan R. Zapata
IPC分类号： G06F9/00 , G06F13/00 , G06F12/06
CPC分类号： G06F12/0646 , G06F11/3051 , G11C5/04 , G11C7/1066 , G11C7/1093 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.
摘要翻译：提供了用于改善对应于多个存储器模块的存储器训练结果的方法，装置和计算机程序产品。实施例包括在启动包括多个存储器模块的系统的引导顺序时检测硬件配置变化; 产生多个训练迭代，对应于数据选通（DQS）信号与所述多个存储器模块的数据有效数据（DQ）行窗口的对准的参考训练值; 识别每个训练迭代，为该训练迭代生成的参考训练值内的任何外部值; 从参考训练值中消除所识别的外部值; 基于剩余参考训练值的平均值生成最终参考训练值; 并使用最终参考训练值作为系统引导顺序的DQ-DQS定时值。

2. 发明授权

US08102651B2 Airflow barriers for efficient cooling of memory modules 有权
标题翻译：用于高效冷却内存模块的气流屏障
公开(公告)号：US08102651B2
公开(公告)日：2012-01-24
申请号：US12572301
申请日：2009-10-02
申请人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, Sr. , Ivan R. Zapata
发明人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, Sr. , Ivan R. Zapata
IPC分类号： H05K7/20
CPC分类号： G06F1/20
摘要： Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.
摘要翻译：提供通过包括存储器模块的上游列和存储器模块的下游列的底盘的气流的方法和装置。气流被分为从上游塔的上游端延伸到下游塔的下游端的第一和第二分开的气流。第一气流引导与可操作地安装在上游塔中的单个存储器模块接触，并且避免与下游塔中的任何存储器模块接触。引导第二气流流以避免与上游塔中的任何存储器模块接触并与可操作地安装在下游塔中的单个存储器模块接触。即使在这样的存储器模块上的热负载较大，改进的冷却也能够每通道扩展使用单个存储器模块。结果是总体上节省了电力，因为冷却要求不再要求每个通道安装额外的内存模块，以便共享和分配热负载。

3. 发明授权

US08432027B2 Integrated circuit die stacks with rotationally symmetric vias 有权
标题翻译：具有旋转对称通孔的集成电路芯片堆叠
公开(公告)号：US08432027B2
公开(公告)日：2013-04-30
申请号：US12616563
申请日：2009-11-11
申请人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
IPC分类号： H01L23/538 , H01L23/48
CPC分类号： H01L23/5384 , H01L21/822 , H01L25/0657 , H01L2224/16 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555
摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, rotated with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are rotationally symmetrical with respect to the TSVs and PTVs on the other identical die.
摘要翻译：一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及第一集成电路管芯，与第一管芯相同，相对于第一管芯旋转并且安装在第一管芯上，第一管芯中的PTV将信号线从衬底通过第一管芯连接到硅通孔（“ TSV），其通过连接到第二管芯上的电子电路的第二管芯的导电通路构成; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一相同管芯上的TSV和PTV旋转对称。

4. 发明授权

US08315068B2 Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same 有权
标题翻译：集成电路芯片堆叠具有最初相同的裸片，其具有熔丝和其制造方法
公开(公告)号：US08315068B2
公开(公告)日：2012-11-20
申请号：US12616912
申请日：2009-11-12
申请人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
IPC分类号： H05K1/11 , H05K1/14
CPC分类号： H01L23/481 , H01L23/5256 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
摘要翻译：集成电路芯片堆叠，其具有安装在基板上的第一裸片，所述第一模具被制造成与具有多个穿通硅通孔（TSV）的第二裸片最初相同，所述第一裸片通过在第一裸片上熔化熔丝而被个性化，先前通过熔断保险丝连接的TSV通过通孔（PTV），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具在第二次死亡时死于TSV。

5. 发明授权

US07741736B2 System and method for multiple sense point voltage regulation 失效
标题翻译：多感测点电压调节系统和方法
公开(公告)号：US07741736B2
公开(公告)日：2010-06-22
申请号：US11869116
申请日：2007-10-09
申请人： Raymond M. Clemo , Jimmy G. Foster, Sr. , Suzanne M. Michelich , Sheldon J. Sigrist , Jacques B. Taylor
发明人： Raymond M. Clemo , Jimmy G. Foster, Sr. , Suzanne M. Michelich , Sheldon J. Sigrist , Jacques B. Taylor
IPC分类号： H01H83/00
CPC分类号： H02J1/14 , G06F1/26 , Y10T307/406 , Y10T307/858
摘要： The present invention is a system and method for sensing the voltage at multiple sense points. The present invention acquires optimal feedback from a plurality of sources including those integrated on the same motherboard, for populated or unpopulated connectors and for adapter cards plugged into the connectors, for the purpose of controlling the voltage regulator output. The voltage regulator, connected to a logic system, provides voltage to those connectors needing the voltage.
摘要翻译：本发明是用于感测多个感测点处的电压的系统和方法。为了控制电压调节器输出，本发明从多个源获得包括集成在同一主板上的最佳反馈，对于填充或未填充的连接器以及插入到连接器中的适配卡。连接到逻辑系统的电压调节器为需要电压的那些连接器提供电压。

6. 发明授权

US07711886B2 Dynamically allocating communication lanes for a plurality of input/output (‘I/O’) adapter sockets in a point-to-point, serial I/O expansion subsystem of a computing system 失效
标题翻译：动态地为计算系统的点对点串行I / O扩展子系统中的多个输入/输出（'I / O'）适配器插座分配通信通道
公开(公告)号：US07711886B2
公开(公告)日：2010-05-04
申请号：US11956026
申请日：2007-12-13
申请人： Jimmy G. Foster, Sr.
发明人： Jimmy G. Foster, Sr.
IPC分类号： G06F13/20 , G06F13/40
CPC分类号： G06F13/409
摘要： Methods, systems, and products are disclosed for dynamically allocating communication lanes for a plurality of sockets in a point-to-point, serial I/O expansion subsystem of a computing system, the expansion subsystem including an switch that supports a maximum number of enabled communication lanes, each socket having a same form factor, each socket connected to the switch using a same predefined number of communication lanes, that include: identifying, during a boot process for the computing system, each of the sockets in which an adapter is installed; determining, for each installed adapter, a maximum link width for that adapter; and enabling, for each of the sockets in which an adapter is installed, a set of communication lanes for communications between the adapter installed in that socket and the expansion subsystem switch in dependence upon the maximum link width for each adapter and the maximum number of enabled communication lanes supported by the switch.
摘要翻译：公开了用于为计算系统的点对点串行I / O扩展子系统中的多个套接字动态分配通信通道的方法，系统和产品，该扩展子系统包括支持最大数目的启用的交换机通信通道，每个插座具有相同的形状因子，每个插座使用相同的预定数量的通信线路连接到交换机，其包括：在计算系统的引导过程期间识别其中安装了适配器的每个插座 ; 为每个安装的适配器确定该适配器的最大链路宽度; 并且对于安装有适配器的每个插座，根据每个适配器的最大链路宽度和启用的最大数量，为安装在该套接字中的适配器和扩展子系统交换机之间的通信提供一组通信通道交换机支持的通信通道。

7. 发明授权

US07347251B2 Heat sink for distributing a thermal load 有权
标题翻译：用于分配热负荷的散热器
公开(公告)号：US07347251B2
公开(公告)日：2008-03-25
申请号：US11314567
申请日：2005-12-21
申请人： Jimmy G. Foster, Sr. , Donna C. Hardee , Don S. Keener , Robert R. Wolford
发明人： Jimmy G. Foster, Sr. , Donna C. Hardee , Don S. Keener , Robert R. Wolford
IPC分类号： F28D15/02
CPC分类号： H01L23/427 , F28D15/0266 , F28F3/02 , H01L23/467 , H01L2924/0002 , H01L2924/00
摘要： A heat sink for distributing a thermal load is disclosed that includes two or more base plates connected and oriented around a central axis of the heat sink, at least one base plate receiving the thermal load, each base plate having thermal transport paths, the thermal transport paths oriented among the base plates so as to have the capability of accepting thermal transports having a plurality of lengths for thermal distribution between at least two base plates, heat-dissipating fins connected to each base plate, the heat-dissipating fins spaced apart in parallel and extending from each base plate towards the central axis of the heat sink, and a thermal transport connected between the base plate receiving the thermal load and at least one other base plate so as to distribute the thermal load among the base plates of the heat sink.
摘要翻译：公开了一种用于分配热负荷的散热器，其包括连接并定向在散热片的中心轴线周围的两个或更多个基板，至少一个接收热负载的基板，每个基板具有热传输路径，热传输在基板之间定向的路径，以便具有接受具有多个长度以用于在至少两个基板之间进行热分配的热传输的能力，连接到每个基板的散热翅片，平行间隔开的散热翅片并且从每个基板朝向散热器的中心轴线延伸，以及连接在接收热负载的基板和至少一个其它基板之间的热传输，以便将热负载分布在散热器的基板中。

8. 发明授权

US09262284B2 Single channel memory mirror 有权
标题翻译：单通道内存镜
公开(公告)号：US09262284B2
公开(公告)日：2016-02-16
申请号：US11567964
申请日：2006-12-07
申请人： William E. Atherton , Jimmy G. Foster, Sr.
发明人： William E. Atherton , Jimmy G. Foster, Sr.
IPC分类号： G06F12/00 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1666 , G06F11/20
摘要： Embodiments of the invention address deficiencies of the art in respect to memory fault tolerance, and provide a novel and non-obvious method, system and apparatus for single channel memory mirroring. In one embodiment of the invention, a single channel memory mirroring system can be provided. The single channel memory mirroring system can include a memory controller, a single communications channel, and an operational data portion of memory, and a duplicate data portion of memory, both portions being communicatively coupled to the memory controller over the single communications channel. Finally, the system can include single channel memory mirror logic. The logic can include program code enabled to mirror data in the operational data portion of memory in the duplicate data portion of memory.
摘要翻译：本发明的实施例解决了存储器容错方面的技术缺陷，并且提供了用于单通道存储器镜像的新颖且非显而易见的方法，系统和装置。在本发明的一个实施例中，可以提供单通道存储器镜像系统。单通道存储器镜像系统可以包括存储器控制器，单个通信信道和存储器的操作数据部分以及存储器的重复数据部分，两个部分通过单个通信信道通信地耦合到存储器控制器。最后，系统可以包括单通道存储器镜像逻辑。逻辑可以包括启用以镜像存储器的重复数据部分中的存储器的操作数据部分中的数据的程序代码。

9. 发明授权

US09076770B2 Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same 有权
标题翻译：集成电路芯片堆叠具有最初相同的裸片，其具有熔丝和其制造方法
公开(公告)号：US09076770B2
公开(公告)日：2015-07-07
申请号：US13569267
申请日：2012-08-08
申请人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
发明人： Jimmy G. Foster, Sr. , Kyu-Hyoun Kim
IPC分类号： H01L23/48 , H01L23/525 , H01L25/065 , H01L25/00 , H01L25/18
CPC分类号： H01L23/481 , H01L23/5256 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.
摘要翻译：具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上吹入保险丝来个性化，将先前通过熔断保险丝连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具在第二次死亡时死于TSV。

10. 发明授权

US08805590B2 Fan speed control of rack devices where sum of device airflows is greater than maximum airflow of rack 有权
标题翻译：机架设备的风扇速度控制，其中设备气流的总和大于机架的最大气流
公开(公告)号：US08805590B2
公开(公告)日：2014-08-12
申请号：US12647357
申请日：2009-12-24
申请人： Sumanta K. Bahali , Vinod Kamath , Jimmy G. Foster, Sr.
发明人： Sumanta K. Bahali , Vinod Kamath , Jimmy G. Foster, Sr.
IPC分类号： G05D7/06
CPC分类号： G05D23/1934 , H05K7/20736 , H05K7/20836
摘要： Computing devices have fan speeds governing airflows through the computing devices. The rack has a maximum airflow associated with a cooling component for the rack. The computing devices transmit their current airflows. A sum of the current airflows is determined. Where the sum is greater than the maximum airflow, the fan speeds of one or more selected computing devices are decreased. The fan speeds of lower priority computing devices may be reduced before the fan speeds higher priority computing devices are reduced. Fan speed reduction may be achieved in a centralized manner, by employing a centralized management component, or in a decentralized manner, without employing a centralized management component.
摘要翻译：计算设备具有控制通过计算设备的气流的风扇速度。机架具有与机架的冷却组件相关的最大气流。计算设备传送其当前气流。确定当前气流的总和。在总和大于最大气流的情况下，减少一个或多个所选计算装置的风扇速度。降低优先级较高的计算设备的风扇速度可能会在风扇转速较高的优先级计算设备减少之前被降低。可以通过采用集中式管理部件或以分散的方式集中地实现风扇减速，而不采用集中式管理部件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式