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1. 发明授权

US11581881B1 Clock and phase alignment between physical layers and controller 有权
公开(公告)号：US11581881B1
公开(公告)日：2023-02-14
申请号：US17405854
申请日：2021-08-18
申请人： XILINX, INC.
发明人： Sarosh I. Azad , Benson Chau , Tomai Knopp
IPC分类号： H03K5/02 , H03K23/60 , H03K19/20 , H03K19/173 , H03K5/00
摘要： An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

2. 发明授权

US10657067B1 Memory management unit with prefetch 有权
公开(公告)号：US10657067B1
公开(公告)日：2020-05-19
申请号：US15262834
申请日：2016-09-12
申请人： Xilinx, Inc.
发明人： Sarosh I. Azad , Bhaarath Kumar
IPC分类号： G06F12/00 , G06F12/1027 , G06F12/0862
摘要： A memory management unit circuit includes a plurality of ports with a plurality of translation buffer units. Each translation buffer unit includes a translation lookaside buffer circuit and a translation logic circuit configured to perform virtual to physical address translation using the translation lookaside buffer circuit. A translation lookaside buffer circuit prefetch logic circuit monitors virtual memory access requests received at the corresponding port of the memory management unit circuit and detects satisfaction of at least one trigger condition. In response, address translation prefetch requests are generated. A control circuit transmits the address translation prefetch requests to a physical memory circuit and receives address translation data for populating the translation lookaside buffer.

3. 发明授权

US10402332B2 Memory pre-fetch for virtual memory 有权
公开(公告)号：US10402332B2
公开(公告)日：2019-09-03
申请号：US15163384
申请日：2016-05-24
申请人： Xilinx, Inc.
发明人： Bhaarath Kumar , Sarosh I. Azad
IPC分类号： G06F12/0862 , G06F12/1027 , G06F12/1009 , G06F13/28
摘要： Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.

4. 发明申请

US20170344482A1 MEMORY PRE-FETCH FOR VIRTUAL MEMORY 审中-公开
公开(公告)号：US20170344482A1
公开(公告)日：2017-11-30
申请号：US15163384
申请日：2016-05-24
申请人： Xilinx, Inc.
发明人： Bhaarath Kumar , Sarosh I. Azad
IPC分类号： G06F12/0862 , G06F13/28 , G06F12/1009 , G06F12/1027
CPC分类号： G06F12/0862 , G06F12/1009 , G06F12/1027 , G06F13/28 , G06F2212/6026 , G06F2212/65 , G06F2212/68
摘要： Virtual memory pre-fetch requests are generated for a virtual memory and a multiple port memory management unit (MMU) circuit. Virtual memory access requests sent to a particular port of the MMU circuit are monitored. In response to the satisfaction of a trigger condition, virtual memory pre-fetch requests are generated and transmitted to the MMU circuit using the particular port. Physical access requests from the MMU circuit are monitored for physical addresses corresponding to the virtual memory pre-fetch requests. The physical access requests corresponding to the virtual memory pre-fetch requests are filtered.

5. 发明授权

US09965417B1 Use of interrupt memory for communication via PCIe communication fabric 有权
公开(公告)号：US09965417B1
公开(公告)日：2018-05-08
申请号：US14995124
申请日：2016-01-13
申请人： Xilinx, Inc.
发明人： Sarosh I. Azad , Sunita Jain
IPC分类号： G06F13/32 , G06F13/16 , G06F13/42 , G06F12/1081
CPC分类号： G06F13/32 , G06F12/1081 , G06F13/1642 , G06F13/4282 , G06F2212/656
摘要： Techniques for communication with a host system via a peripheral component interconnect express (PCIe) communication fabric are disclosed herein. A peripheral device having its own memory address space executes a boot ROM to initialize a PCIe-to internal memory address space bridge and to disable MSIx interrupts. The peripheral device monitors a specific location in memory dedicated to MSIx interrupts for a particular value that indicates that PCIe device enumeration is complete. At this point, the peripheral device knows that its PCIe base address registers have been set by the host, and sets address translation registers for translating addresses in the address space of the host to the address space of the peripheral device.

6. 发明授权

US09465766B1 Isolation interface for master-slave communication protocols 有权
标题翻译：主从通信协议的隔离接口
公开(公告)号：US09465766B1
公开(公告)日：2016-10-11
申请号：US14065804
申请日：2013-10-29
申请人： Xilinx, Inc.
发明人： Tomai Knopp , Sarosh I. Azad , Bhaarath Kumar
IPC分类号： G06F13/36 , G06F13/42
CPC分类号： G06F13/42
摘要： An apparatus for communication using a master-slave communication protocol includes a master circuit and a slave circuit configured to communicate with each other using a master-slave communication protocol. The apparatus also includes an interface circuit coupled to the master and slave circuits. In response to a first control signal having a first value, the interface circuit forwards messages received from the master circuit to the slave circuit and forwards responses received from the slave circuit to the master circuit. In response to the first control signal having a second value, the interface circuit prevents messages received from the master circuit from being forwarded from the master circuit to the slave circuit.
摘要翻译：使用主从通信协议的通信装置包括主电路和被配置为使用主 - 从通信协议彼此通信的从电路。该装置还包括耦合到主电路和从电路的接口电路。响应于具有第一值的第一控制信号，接口电路将从主电路接收的消息转发到从电路，并将从从电路接收的响应转发给主电路。响应于具有第二值的第一控制信号，接口电路防止从主电路接收的消息从主电路转发到从电路。

7. 发明授权

US09411701B2 Analog block and test blocks for testing thereof 有权
标题翻译：模拟块和测试块用于测试
公开(公告)号：US09411701B2
公开(公告)日：2016-08-09
申请号：US13802223
申请日：2013-03-13
申请人： Xilinx, Inc.
发明人： Sarosh I. Azad
IPC分类号： G01R31/3167 , G06F11/27 , G01R31/317
CPC分类号： G06F11/27 , G01R31/3167 , G01R31/3171 , G01R31/31716
摘要： An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.
摘要翻译：公开了一种通常涉及片上系统的装置。在该装置中，片上系统具有至少一个模拟块，输入/输出接口，数据测试块和处理单元。处理单元耦合到输入/输出接口以控制对至少一个模拟块的访问。数据测试块通过输入/输出接口耦合到至少一个模拟块。处理单元耦合到数据测试块并且被配置为执行具有至少一个测试图案的测试代码。在由处理单元执行的测试代码的控制下的数据测试块被配置为用测试图案测试至少一个模拟块。

8. 发明申请

US20160004656A1 BRIDGING INTER-BUS COMMUNICATIONS 有权
标题翻译：桥接通信通信
公开(公告)号：US20160004656A1
公开(公告)日：2016-01-07
申请号：US14325238
申请日：2014-07-07
申请人： Xilinx, Inc.
发明人： Ygal Arbel , Sagheer Ahmad , Sarosh I. Azad
IPC分类号： G06F13/364 , G06F13/40
CPC分类号： G06F13/404 , G06F12/1441 , G06F12/145 , G06F21/78 , G06F21/85
摘要： Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.
摘要翻译：公开了用于桥接第一和第二总线之间的通信的方法。地址转换信息和相关的安全指示符存储在存储器中。来自第一总线的每个访问请求包括第一请求者安全指示符和所请求的地址。基于请求者安全指示符和与所请求地址的地址转换信息相关联的安全指示符，来自第一总线并被引导到第二总线的每个访问请求被拒绝或翻译并传送到第二总线。从第二总线到第一总线的每个访问请求包括所请求的地址，并且访问请求被转换并且与与所请求地址的地址转换信息相关联的安全指示符一起被传送到第一总线。

9. 发明授权

US09148192B1 Transceiver for providing a clock signal 有权
标题翻译：收发器用于提供时钟信号
公开(公告)号：US09148192B1
公开(公告)日：2015-09-29
申请号：US13962468
申请日：2013-08-08
申请人： Xilinx, Inc.
发明人： Alan C. Wong , Christopher J. Borrelli , Loren Jones , Seu Wah Low , Parag Upadhyaya , Robert M. Ondris , Sarosh I. Azad
IPC分类号： H04B1/40
CPC分类号： H04L25/14
摘要： An apparatus relating generally to a transmitter-side of a transceiver or a transmitter used to provide a clock signal is disclosed. In this apparatus, a first signal source is to provide a first periodic signal. A second signal source is to provide a second periodic signal. A first multiplexer is coupled to receive the first periodic signal and the second periodic signal to provide a selected one thereof as a first selected output. A phase interpolator is coupled to the first multiplexer to receive the first selected output. The phase interpolator includes a second multiplexer. The second multiplexer is coupled to receive the first selected output and a phase-interpolated version of the first selected output to output a selected one thereof as a second selected output. A divider is coupled to the second multiplexer to receive the second selected output to provide the clock signal.
摘要翻译：公开了一种与用于提供时钟信号的收发机或发射机的发射机侧有关的装置。在该装置中，第一信号源是提供第一周期信号。第二信号源是提供第二周期信号。第一多路复用器被耦合以接收第一周期性信号和第二周期信号，以将其选定的一个作为第一选择输出。相位插值器耦合到第一多路复用器以接收第一选择的输出。相位插值器包括第二多路复用器。第二多路复用器被耦合以接收第一选择输出和第一选择输出的相位插值版本，以将其选定的一个输出作为第二选择输出。分频器耦合到第二多路复用器以接收第二选择的输出以提供时钟信号。

10. 发明授权

US11947409B2 Parity protection of control registers based on register bit positions 有权
公开(公告)号：US11947409B2
公开(公告)日：2024-04-02
申请号：US17574340
申请日：2022-01-12
申请人： XILINX, INC.
发明人： Sarosh I. Azad , Aditi R. Ganesan
IPC分类号： G06F11/10 , G06F11/07
CPC分类号： G06F11/0751 , G06F11/0772 , G06F11/1004
摘要： An integrated circuit (IC) device for detecting errors within a register, the IC device includes registers and parity checking circuitry. The parity checking circuitry is coupled to the registers and comprises a first parity circuitry, a second parity circuit, and error detection circuitry. The first parity circuit receives first register values from the registers and determine a first value from the first register values. The second parity circuit is receives second register values from the registers and determines a second value from the second register values. The error detection circuitry compares the first value and the second value to detect a first error within the registers, and output an error signal indicating the first error.

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