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    • 2. 发明申请
    • Method and Apparatus for Performing a CRC Check
    • 执行CRC校验的方法和装置
    • US20120278690A1
    • 2012-11-01
    • US13546180
    • 2012-07-11
    • Xiao-an WangJens Berkmann
    • Xiao-an WangJens Berkmann
    • H03M13/09G06F11/10
    • H03M13/091
    • A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments. The apparatus further includes a plurality of first CRC check units, wherein each of the first CRC check units is configured to perform a first CRC check of a respective one of the plurality of data segments, the plurality of first CRC checks being performed concurrently, and wherein each of the first CRC check units is configured to perform a second CRC check based on an output of the respective first CRC check unit.
    • 给出了一种包括被配置为接收数据流并将接收的数据流划分成多个数据段的分割单元的装置的描述。 该装置还包括多个第一CRC校验单元,其中第一CRC校验单元中的每一个被配置为执行多个数据段中的相应一个数据段的第一CRC校验,多个第一CRC校验同时执行,以及 其中,所述第一CRC校验单元中的每一个被配置为基于相应的第一CRC校验单元的输出执行第二CRC校验。
    • 3. 发明授权
    • Method and apparatus for performing a CRC check
    • 用于执行CRC校验的方法和装置
    • US09106259B2
    • 2015-08-11
    • US13546180
    • 2012-07-11
    • Xiao-an WangJens Berkmann
    • Xiao-an WangJens Berkmann
    • G06F11/10H03M13/00H03M13/09
    • H03M13/091
    • A description is given of an apparatus that includes a division unit configured to receive a data stream and to divide the received data stream into a plurality of data segments. The apparatus further includes a plurality of first CRC check units, wherein each of the first CRC check units is configured to perform a first CRC check of a respective one of the plurality of data segments, the plurality of first CRC checks being performed concurrently, and wherein each of the first CRC check units is configured to perform a second CRC check based on an output of the respective first CRC check unit.
    • 给出了一种包括被配置为接收数据流并将接收的数据流划分成多个数据段的分割单元的装置的描述。 该装置还包括多个第一CRC校验单元,其中第一CRC校验单元中的每一个被配置为执行多个数据段中的相应一个数据段的第一CRC校验,多个第一CRC校验同时执行,以及 其中,所述第一CRC校验单元中的每一个被配置为基于相应的第一CRC校验单元的输出执行第二CRC校验。
    • 5. 发明申请
    • WORKER AND ITERATION CONTROL FOR PARALLEL TURBO DECODER
    • 并行涡轮解码器的工作和迭代控制
    • US20140064413A1
    • 2014-03-06
    • US13599943
    • 2012-08-30
    • Axel HuebnerJens BerkmannMaria FresiaArmin Hautle
    • Axel HuebnerJens BerkmannMaria FresiaArmin Hautle
    • H04L27/00
    • H03M13/1111H03M13/2957H03M13/3715H03M13/3972H03M13/6508H03M13/6516
    • A device such as a worker, window-size and iteration control unit (WWICU) is proposed. The WWICU determines processing, iteration, and window information based on format information indicative of one or more formats to be processed by a decoding process. The processing information may include a number of parallel workers, the iteration information may include a number of half-iterations, and the window information may include a window size to be used in the decoding process. The WWICU then determines time information including a total cycle count based on the processing information, the iteration information, and the window information. In response to determining that the total cycle count is not beyond a threshold value, the WWICU may transmit configuration information including the processing, iteration, and window information to a device, such as a turbo decoding device, configurable to perform the decoding process based on the configuration information.
    • 提出了诸如工作者,窗口大小和迭代控制单元(WWICU)等设备。 WWICU基于指示要由解码处理处理的一种或多种格式的格式信息来确定处理,迭代和窗口信息。 处理信息可以包括多个并行工作者,迭代信息可以包括多个半迭代,并且窗口信息可以包括要在解码过程中使用的窗口大小。 然后,WWICU基于处理信息,迭代信息和窗口信息来确定包括总周期数的时间信息。 响应于确定总周期计数不超过阈值,WWICU可以将包括处理,迭代和窗口信息的配置信息发送到诸如turbo解码设备的设备,其可配置为基于 配置信息。
    • 7. 发明授权
    • Decoder of error correction codes
    • 解码器的纠错码
    • US08190977B2
    • 2012-05-29
    • US12199414
    • 2008-08-27
    • Michael LunglmayrJens Berkmann
    • Michael LunglmayrJens Berkmann
    • H03M13/00
    • H03M13/1191H03M13/1105H03M13/1108H03M13/13H03M13/3784H03M13/451H03M13/458H03M13/616H03M13/6362H04L1/0045H04L1/0057
    • In a method of decoding data symbols into codewords, reliability information of the data symbols is provided. A first group of symbols from a first set of groups of symbols is selected, wherein the first set of groups of symbols is defined by at least a first parity-check of a parity-check matrix of a linear block code which has been used to encode the data symbols. The selection is based on the reliability information. A second group of symbols from a second set of groups of symbols is selected, wherein the second set of groups of symbols is defined by at least a second parity-check of the parity-check matrix. The selection is based on the selected first group of symbols and the reliability information. At least a part of the codeword is composed on the basis of the first group of symbols and the second group of symbols.
    • 在将数据符号解码成码字的方法中,提供数据符号的可靠性信息。 选择来自第一组符号组的第一组符号,其中所述第一组符号组由至少已被使用于线性块码的奇偶校验矩阵的奇偶校验矩阵的第一奇偶校验来确定 对数据符号进行编码。 选择是基于可靠性信息。 选择来自第二组符号组的第二组符号,其中通过奇偶校验矩阵的至少第二奇偶校验来确定第二组符号组。 该选择基于所选择的第一组符号和可靠性信息。 码字的至少一部分是基于第一组符号和第二组符号构成的。
    • 9. 发明授权
    • Reduced contention storage for channel coding
    • 减少争用存储,用于通道编码
    • US09130728B2
    • 2015-09-08
    • US12485626
    • 2009-06-16
    • Jens BerkmannAxel Huebner
    • Jens BerkmannAxel Huebner
    • G06F12/00G06F13/00G06F13/28H04L1/00H03M13/29H03M13/39H03M13/00G06F12/06
    • H04L1/0071G06F12/0607H03M13/2903H03M13/2957H03M13/3972H03M13/653H03M13/6566H04L1/005H04L1/0052H04L1/0066
    • A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.
    • 用于解码级联代码的解码器包括用于使用存储交错操作对接收到的数据进行存储交错的存储输入交织器。 数据存储器耦合到存储输入交织器的输出端,用于存储交错数据的临时存储。 第一存储输出交织器耦合到数据存储器的输出,用于交错从数据存储器读取的数据,并且多个处理器耦合到第一存储输出交织器的输出以访问数据存储器。 此外,用于产生级联代码序列的编码器包括耦合到编码器的输入端的代码交织器,用于施加代码生成交织操作,第一卷积编码器具有耦合到代码交织器的输出的输入端和耦合到存储交织器 涉及用于应用存储交错操作的编码器的输入。
    • 10. 发明申请
    • METHOD AND APPARATUS FOR TURBO DECODER MEMORY COLLISION RESOLUTION
    • TURBO解码器存储器碰撞分辨率的方法和装置
    • US20140068117A1
    • 2014-03-06
    • US13599926
    • 2012-08-30
    • Axel HuebnerJens BerkmannMichael Janning
    • Axel HuebnerJens BerkmannMichael Janning
    • G06F3/00
    • G06F13/16G06F13/1673G06F13/376G06F13/38H03M13/2775H03M13/2957
    • A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.
    • 提出了诸如turbo解码装置的装置,其中包括地址缓冲装置和元素缓冲装置的中间缓冲装置通信地耦合到多个处理装置和存储装置。 在并行解码处理的周期期间,中间缓冲装置从两个不同的处理装置接收分别对应于存储在存储装置中的代码序列的第一和第二元素的第一和第二地址信息。 在该循环期间,中间缓冲装置基于第一地址信息向存储装置发送对第一元素的请求,并将第二地址信息存储在地址缓冲装置中。 随后,在该周期期间,中间缓冲装置从存储装置接收对应于第一元素的第一元素信息,并将接收到的第一元素信息存储在元素缓存装置中。