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1. 发明授权

US08081095B2 Data output circuit 有权
标题翻译：数据输出电路
公开(公告)号：US08081095B2
公开(公告)日：2011-12-20
申请号：US12134525
申请日：2008-06-06
申请人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
发明人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
IPC分类号： H03M9/00
CPC分类号： G09G3/3685
摘要： A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.
摘要翻译：数据输出电路包括：数据产生电路，被配置为产生输出数据; 以及串行输出电路，被配置为接收对应于数据产生电路的地址，在接收地址的时间段内保持并行数据输入，并且串行输出由数据产生电路产生的输出数据和所保持的并行根据用于引导数据输出的输出方向信号的数据。

2. 发明申请

US20080303761A1 Data Output Circuit 有权
标题翻译：数据输出电路
公开(公告)号：US20080303761A1
公开(公告)日：2008-12-11
申请号：US12134525
申请日：2008-06-06
申请人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
发明人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
IPC分类号： G09G3/36
CPC分类号： G09G3/3685
摘要： A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.
摘要翻译：数据输出电路包括：数据产生电路，被配置为产生输出数据; 以及串行输出电路，被配置为接收对应于数据产生电路的地址，在接收地址的时间段内保持并行数据输入，并且串行输出由数据产生电路产生的输出数据和所保持的并行根据用于引导数据输出的输出方向信号的数据。

3. 发明授权

US08238385B2 Data processing circuit and data processing method 有权
标题翻译：数据处理电路和数据处理方法
公开(公告)号：US08238385B2
公开(公告)日：2012-08-07
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/04
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译：一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。

4. 发明申请

US20080019400A1 Data Processing Circuit and Data Processing Method 有权
标题翻译：数据处理电路和数据处理方法
公开(公告)号：US20080019400A1
公开(公告)日：2008-01-24
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/06 , G06F1/00
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译：一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。

5. 发明授权

US08082375B2 Noise-tolerant data communication system 有权
标题翻译：耐噪数据通信系统
公开(公告)号：US08082375B2
公开(公告)日：2011-12-20
申请号：US12186149
申请日：2008-08-05
申请人： Tetsuya Tokunaga , Yoshiyuki Yamagata , Yasuo Osawa , Kensuke Goto
发明人： Tetsuya Tokunaga , Yoshiyuki Yamagata , Yasuo Osawa , Kensuke Goto
IPC分类号： G06F3/00 , G06F1/12
CPC分类号： G06F1/12 , G06F13/4291
摘要： This invention offers a data communication system that can perform data communication and detection of a data read-in request signal while reducing the number of communication lines to three, and is tolerant of noise. The data communication between a microcomputer and a key scan IC and the detection of the data read-in request signal are performed through a control line, a clock line and a data line. The data communication system is provided with a data line control circuit that controls the data line so that outputting of the data read-in signal RDRQ to the data line is disabled when first command data is inputted to the key scan IC through the data line, and that the outputting of the data read-in request signal RDRQ to the data line is enabled when second command data is inputted from the microcomputer to the key scan IC through the data line.
摘要翻译：本发明提供了一种数据通信系统，其可以在将通信线路的数量减少到三个的同时执行数据读取请求信号的数据通信和检测，并且容忍噪声。通过控制线，时钟线和数据线来执行微型计算机与键扫描IC之间的数据通信以及数据读入请求信号的检测。数据通信系统设置有数据线控制电路，其控制数据线，使得当通过数据线将第一命令数据输入到键扫描IC时，数据读取信号RDRQ向数据线的输出被禁止，并且当通过数据线从微型计算机向键扫描IC输入第二命令数据时，能够将数据读入请求信号RDRQ输出到数据线。

6. 发明申请

US20090140969A1 LIQUID CRYSTAL DISPLAY DRIVE CIRCUIT 有权
标题翻译：液晶显示驱动电路
公开(公告)号：US20090140969A1
公开(公告)日：2009-06-04
申请号：US12274645
申请日：2008-11-20
申请人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
发明人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
IPC分类号： G09G3/36
CPC分类号： G09G3/18 , G09G3/04 , G09G2310/0245 , G09G2310/06 , G09G2310/08 , G09G2330/02
摘要： This invention offers an LCD drive circuit that prevents conversion to a wrong duty driving state and an unintended display caused by taking in of serial data corresponding to the wrong duty driving state. The LCD drive circuit is provided with an LCD drive signal generation circuit that generates driving signals to turn LCD segments on and off based on serial data received by a serial data receiving circuit and is switchable between a ¼ duty driving state and a ⅓ duty driving state. The LCD drive circuit is also provided with a driving state setting circuit that sets the LCD drive signal generation circuit to the ¼ duty driving state based on identification data when the serial data receiving circuit receives the serial data corresponding to the ¼ duty driving state and thereafter forbids the LCD drive signal generation circuit to take in serial data corresponding to the ⅓ duty driving state when the serial data receiving circuit receives the serial data corresponding to the ⅓ duty driving state.
摘要翻译：本发明提供了一种LCD驱动电路，其防止转换为错误的占空比驱动状态，以及通过接收与错误的占空比驱动状态相对应的串行数据而引起的非预期显示。 LCD驱动电路配备有LCD驱动信号发生电路，该电路根据串行数据接收电路所接收的串行数据产生驱动信号，使LCD段导通和关断，并且可在1/4负载驱动状态和1/3负载之间切换驾驶状态 LCD驱动电路还设置有驱动状态设置电路，当串行数据接收电路接收到对应于¼占空比驱动状态的串行数据时，基于识别数据将LCD驱动信号发生电路设置为¼占空比驱动状态当串行数据接收电路接收到对应于1/3占空比驱动状态的串行数据时，禁止LCD驱动信号发生电路采取对应于1/3占空比驱动状态的串行数据。

7. 发明申请

US20080218389A1 Serial-To-Parallel Converter Circuit and Liquid Crystal Display Driving Circuit 有权
标题翻译：串行到并行转换器电路和液晶显示驱动电路
公开(公告)号：US20080218389A1
公开(公告)日：2008-09-11
申请号：US12044867
申请日：2008-03-07
申请人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
发明人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G09G3/2096 , G09G3/3688 , G09G2310/08
摘要： A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (
摘要翻译：一种串并转换器电路，包括：m位串行数据保持单元，用于输入其输入位数设置为m或传输周期内的n（

8. 发明授权

US07619547B2 Serial-to-parallel converter circuit and liquid crystal display driving circuit 有权
标题翻译：串并转换电路和液晶显示驱动电路
公开(公告)号：US07619547B2
公开(公告)日：2009-11-17
申请号：US12044867
申请日：2008-03-07
申请人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
发明人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G09G3/2096 , G09G3/3688 , G09G2310/08
摘要： A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (
摘要翻译：一种串并转换器电路，包括：m位串行数据保持单元，用于输入其输入位数设置为m或传输周期内的n（

9. 发明授权

US08154496B2 Liquid crystal display drive circuit 有权
标题翻译：液晶显示驱动电路
公开(公告)号：US08154496B2
公开(公告)日：2012-04-10
申请号：US12274645
申请日：2008-11-20
申请人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
发明人： Yoshiyuki Yamagata , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto
IPC分类号： G09G3/36
CPC分类号： G09G3/18 , G09G3/04 , G09G2310/0245 , G09G2310/06 , G09G2310/08 , G09G2330/02
摘要： This invention offers an LCD drive circuit that prevents conversion to a wrong duty driving state and an unintended display caused by taking in of serial data corresponding to the wrong duty driving state. The LCD drive circuit is provided with an LCD drive signal generation circuit that generates driving signals to turn LCD segments on and off based on serial data received by a serial data receiving circuit and is switchable between a ¼ duty driving state and a ⅓ duty driving state. The LCD drive circuit is also provided with a driving state setting circuit that sets the LCD drive signal generation circuit to the ¼ duty driving state based on identification data when the serial data receiving circuit receives the serial data corresponding to the ¼ duty driving state and thereafter forbids the LCD drive signal generation circuit to take in serial data corresponding to the ⅓ duty driving state when the serial data receiving circuit receives the serial data corresponding to the ⅓ duty driving state.
摘要翻译：本发明提供了一种LCD驱动电路，其防止转换为错误的占空比驱动状态，以及通过接收与错误的占空比驱动状态相对应的串行数据而引起的非预期显示。 LCD驱动电路设置有LCD驱动信号发生电路，其根据由串行数据接收电路接收到的串行数据产生驱动信号以使LCD段导通和关断，并且可在¼负载驱动状态和÷占空比驱动状态之间切换。 LCD驱动电路还设置有驱动状态设置电路，当串行数据接收电路接收到对应于¼占空比驱动状态的串行数据时，基于识别数据将LCD驱动信号发生电路设置为¼占空比驱动状态禁止LCD驱动信号发生电路在串行数据接收电路接收到与占空比驱动状态相对应的串行数据时，获取对应于三位负荷驱动状态的串行数据。

10. 发明授权

US08018445B2 Serial data input system 有权
标题翻译：串行数据输入系统
公开(公告)号：US08018445B2
公开(公告)日：2011-09-13
申请号：US11542640
申请日：2006-10-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G11C7/02 , G11C7/1036 , G11C7/1078 , G11C7/1087
摘要： Increase in power consumption and increase in power supply noise of a serial data input system are suppressed, while clock skew is more easily prevented. The serial data input system of this invention includes a shift register that takes in and shifts serially transferred display data in synchronization with a clock SCL, a clock counter that counts the number of clock pulses of the clock SCL and outputs each of clock count signals BIT08, BIT16 and BIT24 when the counted number of the clock pulses of the clock SCL reaches each of count numbers 8, 16 and 24 respectively, and registers into each of which the data stored in the shift register is transferred and stored collectively and in parallel in response to each of the clock count signals BIT08, BIP16 and BIT24 respectively.
摘要翻译：抑制串行数据输入系统的功耗增加和电源噪声增加，同时更容易防止时钟偏移。本发明的串行数据输入系统包括一个移位寄存器，其与时钟SCL同步地接收和移位串行传送的显示数据，时钟计数器对时钟SCL的时钟脉冲数进行计数，并输出每个时钟计数信号BIT08 ，BIT16和BIT24，当时钟SCL的时钟脉冲的计数数量分别达到计数数8,16和24的每一个时，并且寄存到每个存储在移位寄存器中的数据被共同并且并行存储分别响应于每个时钟计数信号BIT08，BIP16和BIT24。

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