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1. 发明授权

US08081095B2 Data output circuit 有权
标题翻译：数据输出电路
公开(公告)号：US08081095B2
公开(公告)日：2011-12-20
申请号：US12134525
申请日：2008-06-06
申请人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
发明人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
IPC分类号： H03M9/00
CPC分类号： G09G3/3685
摘要： A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.
摘要翻译：数据输出电路包括：数据产生电路，被配置为产生输出数据; 以及串行输出电路，被配置为接收对应于数据产生电路的地址，在接收地址的时间段内保持并行数据输入，并且串行输出由数据产生电路产生的输出数据和所保持的并行根据用于引导数据输出的输出方向信号的数据。

2. 发明申请

US20080303761A1 Data Output Circuit 有权
标题翻译：数据输出电路
公开(公告)号：US20080303761A1
公开(公告)日：2008-12-11
申请号：US12134525
申请日：2008-06-06
申请人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
发明人： Yasuo Osawa , Hiroyuki Arai , Tetsuya Tokunaga , Yoshiyuki Yamagata
IPC分类号： G09G3/36
CPC分类号： G09G3/3685
摘要： A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.
摘要翻译：数据输出电路包括：数据产生电路，被配置为产生输出数据; 以及串行输出电路，被配置为接收对应于数据产生电路的地址，在接收地址的时间段内保持并行数据输入，并且串行输出由数据产生电路产生的输出数据和所保持的并行根据用于引导数据输出的输出方向信号的数据。

3. 发明授权

US08238385B2 Data processing circuit and data processing method 有权
标题翻译：数据处理电路和数据处理方法
公开(公告)号：US08238385B2
公开(公告)日：2012-08-07
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/04
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译：一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。

4. 发明申请

US20080019400A1 Data Processing Circuit and Data Processing Method 有权
标题翻译：数据处理电路和数据处理方法
公开(公告)号：US20080019400A1
公开(公告)日：2008-01-24
申请号：US11778947
申请日：2007-07-17
申请人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
发明人： Hiroyuki Arai , Tetsuya Tokunaga , Yasuo Osawa , Kensuke Goto , Yoshiyuki Yamagata , Takeshi Kimura
IPC分类号： H04J3/06 , G06F1/00
CPC分类号： H04L7/02
摘要： A data processing circuit comprising: a first circuit configured to time-division-multiplex a first digital signal synchronous with a clock signal input from an external controller and a second digital signal asynchronous with the clock signal; and a second circuit configured to output a digital signal time-division-multiplexed by the first circuit to the controller.
摘要翻译：一种数据处理电路，包括：第一电路，被配置为对与从外部控制器输入的时钟信号同步的第一数字信号和与时钟信号异步的第二数字信号进行时分复用; 以及第二电路，被配置为将由第一电路进行时分复用的数字信号输出到控制器。

5. 发明授权

US08018445B2 Serial data input system 有权
标题翻译：串行数据输入系统
公开(公告)号：US08018445B2
公开(公告)日：2011-09-13
申请号：US11542640
申请日：2006-10-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G11C7/02 , G11C7/1036 , G11C7/1078 , G11C7/1087
摘要： Increase in power consumption and increase in power supply noise of a serial data input system are suppressed, while clock skew is more easily prevented. The serial data input system of this invention includes a shift register that takes in and shifts serially transferred display data in synchronization with a clock SCL, a clock counter that counts the number of clock pulses of the clock SCL and outputs each of clock count signals BIT08, BIT16 and BIT24 when the counted number of the clock pulses of the clock SCL reaches each of count numbers 8, 16 and 24 respectively, and registers into each of which the data stored in the shift register is transferred and stored collectively and in parallel in response to each of the clock count signals BIT08, BIP16 and BIT24 respectively.
摘要翻译：抑制串行数据输入系统的功耗增加和电源噪声增加，同时更容易防止时钟偏移。本发明的串行数据输入系统包括一个移位寄存器，其与时钟SCL同步地接收和移位串行传送的显示数据，时钟计数器对时钟SCL的时钟脉冲数进行计数，并输出每个时钟计数信号BIT08 ，BIT16和BIT24，当时钟SCL的时钟脉冲的计数数量分别达到计数数8,16和24的每一个时，并且寄存到每个存储在移位寄存器中的数据被共同并且并行存储分别响应于每个时钟计数信号BIT08，BIP16和BIT24。

6. 发明授权

US06246388B1 Display driving circuit for displaying character on display panel 有权
标题翻译：显示面板显示字符显示驱动电路
公开(公告)号：US06246388B1
公开(公告)日：2001-06-12
申请号：US09309035
申请日：1999-05-10
申请人： Syuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
发明人： Syuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
IPC分类号： G09G336
CPC分类号： G09G5/222 , G09G3/04 , G09G3/20 , G09G2310/0278
摘要： For changing the content of a display RAM (38) or an accessory RAM (39), various data SDI, such as an instruction code, address data, display data, is initially transferred to a shift register (11). Then, the display data in the shift register (11) is latched by a latch circuit (62). A write operation is carried out during a period from the completion of a shift operation by the shift register (11) using various data SDI in connection with the current display to the completion of a shift operation using various data SDI in connection with the next display, i.e., a period with an operation enable signal CE remaining at an L or H level. As a result, time allowance for writing is ensured, which contributes to reduction of software processing load by an external device.
摘要翻译：为了更改显示RAM（38）或附件RAM（39）的内容，初始地将诸如指令代码，地址数据，显示数据的各种数据SDI传送到移位寄存器（11）。然后，移位寄存器（11）中的显示数据由锁存电路（62）锁存。在使用与当前显示相关联的各种数据SDI的移位寄存器（11）完成移位操作期间执行写入操作，使用与下一个显示相关联的各种数据SDI的移位操作完成，即具有操作使能信号CE保持在L或H电平的周期。结果，确保写入的时间容许，这有助于减少外部设备的软件处理负担。

7. 发明授权

US07724060B2 Interface circuit and a clock output method therefor 有权
标题翻译：接口电路及其时钟输出方法
公开(公告)号：US07724060B2
公开(公告)日：2010-05-25
申请号：US11736913
申请日：2007-04-18
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Shuji Motegi , Takeshi Hibino , Takeshi Kimura
IPC分类号： G05F1/04 , H03K3/00
CPC分类号： G06F1/04
摘要： An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.
摘要翻译：一个接口电路，响应于用于输出时钟信号的控制信号和从一个逻辑电平到另一个逻辑电平的数据的变化，输出时钟信号和数据到数据寄存器，配置为与时钟信号同步地串行读取数据逻辑电平，所述接口电路包括时钟输出电路，所述时钟输出电路被配置为：当所述控制信号从所述一个逻辑电平改变到另一逻辑电平时，检测所述时钟信号的逻辑电平; 当检测到时钟信号的一个逻辑电平时，将时钟信号原样输出到数据寄存器; 并且当检测到时钟信号的另一个逻辑电平时，在从另一个逻辑电平变为一个逻辑电平之后输出时钟信号到数据寄存器。

8. 发明申请

US20060033583A1 Frequency adjustment circuit 有权
标题翻译：频率调节电路
公开(公告)号：US20060033583A1
公开(公告)日：2006-02-16
申请号：US11196512
申请日：2005-08-04
申请人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
发明人： Tetsuya Tokunaga , Hiroyuki Arai , Takeshi Kimura , Ryouichi Ando , Mamoru Yamaguchi
IPC分类号： H03L7/00
CPC分类号： H03K3/0231 , H03K2005/00084
摘要： A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.
摘要翻译：提供即使在由于外部噪声而使切换电路的频率调整数据变化的情况下也能够维持目标频率的频率调整电路。频率调整电路包括复位信号生成电路，频率调整数据锁存电路，其锁存并保持由第一切换电路产生的频率调整数据ZP 1和ZP 2，以及基于锁存时钟ZCLK和锁存器的第二切换电路时钟生成电路，生成锁存时钟ZCLK。复位信号产生电路产生与从接口电路产生的使能信号EN的上升同步的周期性复位信号ZRES。锁存时钟产生电路产生与使能信号EN的下降同步的锁存时钟ZCLK。

9. 发明授权

US06653999B2 Integrated circuit for driving liquid crystal 有权
标题翻译：用于驱动液晶的集成电路
公开(公告)号：US06653999B2
公开(公告)日：2003-11-25
申请号：US09460171
申请日：1999-12-10
申请人： Shuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
发明人： Shuji Motegi , Hiroyuki Arai , Tetsuya Tokunaga
IPC分类号： G09G336
CPC分类号： G09G3/3696 , G09G2320/0606 , G09G2320/066
摘要： A liquid crystal driving integrated circuit capable of adjusting display contrast and requiring no externally attached components. A resistor formed by four serially connected resistor elements R1 has one end connected to a reference voltage VLCD0 applied from an operational amplifier 8, and the other end connected to an external variable resistor 25 through a terminal 24. Consequently, liquid crystal driving voltages VLCD0, VLCD1, VLCD2, VLCD3, and VLCD4 can be finely adjusted not only by eleven versions of reference voltage VLCD0 in accordance with voltages at respective connection points of twelve serially connected resistor elements, but by changing the resistance of the external variable resistor 25, to thereby provide a liquid crystal driving integrated circuit 1 that can be used for a variety of general purposes. Since only one external variable resistor 25 is required and this resistor is inherently variable, there is no need to consider variation in characteristics.
摘要翻译：一种液晶驱动集成电路，能够调节显示对比度并且不需要外部连接的部件。由四个串联的电阻元件R1形成的电阻器的一端连接到从运算放大器8施加的参考电压VLCD0，另一端通过端子24连接到外部可变电阻器25.因此，液晶驱动电压VLCD0， VLCD1，VLCD2，VLCD3和VLCD4可以根据十二个串联电阻元件的各个连接点处的电压，而是通过改变外部可变电阻器25的电阻，而不仅仅是参考电压VLCD0的十一个版本，从而提供可用于各种通用目的的液晶驱动集成电路1。由于仅需要一个外部可变电阻器25，并且该电阻器是固有的可变的，所以不需要考虑特性的变化。

10. 发明授权

US07379036B2 Driving circuit for vacuum fluorescent display 有权
标题翻译：真空荧光显示驱动电路
公开(公告)号：US07379036B2
公开(公告)日：2008-05-27
申请号：US10808589
申请日：2004-03-25
申请人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
发明人： Hiroyuki Arai , Syuji Motegi , Takeshi Kimura , Tetsuya Tokunaga
IPC分类号： G09G3/22
CPC分类号： G09G3/22 , G09G2330/08
摘要： A driving circuit for a vacuum fluorescent display for pulse-driving a filament of the vacuum fluorescent display with a pulse voltage. The driving circuit comprises a detecting unit for detecting that the level of the pulse voltage is fixed, and outputs a detection signal indicative of the result of the detection. Preferably, the driving circuit comprises a control unit for controlling at least one output of the outputs of the filament driving unit, the grid driving unit and the segment driving unit in order to terminate the driving of at least one of the filament, the grid electrode and the segment electrode, based on the detection signal.
摘要翻译：一种用于以脉冲电压脉冲驱动真空荧光显示器的灯丝的真空荧光显示器的驱动电路。驱动电路包括用于检测脉冲电压的电平是固定的检测单元，并且输出表示检测结果的检测信号。优选地，驱动电路包括用于控制灯丝驱动单元，电网驱动单元和段驱动单元的输出的至少一个输出的控制单元，以便终止至少一个灯丝，栅极和段电极，基于检测信号。

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