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1. 发明申请

US20140003181A1 MEMORY CELL WITH IMPROVED WRITE MARGIN 有权
标题翻译：具有改进的写字符的存储单元
公开(公告)号：US20140003181A1
公开(公告)日：2014-01-02
申请号：US13997633
申请日：2012-03-30
申请人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
发明人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

2. 发明授权

US09111600B2 Memory cell with improved write margin 有权
标题翻译：具有改善写入容限的存储单元
公开(公告)号：US09111600B2
公开(公告)日：2015-08-18
申请号：US13997633
申请日：2012-03-30
申请人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
发明人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
IPC分类号： G11C7/00 , G11C5/14 , G11C11/413
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

3. 发明授权

US09478273B2 Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory 有权
标题翻译：用于改善非易失性存储器的读和写操作的低电阻位线和源极线设备
公开(公告)号：US09478273B2
公开(公告)日：2016-10-25
申请号：US14129506
申请日：2013-10-31
申请人： Cyrille Dray , Blake C. Lin , Fatih Hamzaoglu , Liqiong Wei , Yih Wang
发明人： Cyrille Dray , Blake C. Lin , Fatih Hamzaoglu , Liqiong Wei , Yih Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G06F3/0604 , G06F3/0659 , G06F3/067 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1697
摘要： Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
摘要翻译：描述了一种用于提高读写余量的装置。该装置包括：源线; 第一个位线一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。还描述了一种装置，其包括：源线; 有位一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

4. 发明授权

US09455011B2 Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current 有权
标题翻译：基于脉冲读取电流读取基于磁隧道结（MTJ）的存储单元的方法和系统
公开(公告)号：US09455011B2
公开(公告)日：2016-09-27
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/00 , G11C11/16 , G11C5/12 , G11C13/00
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

5. 发明申请

US20150206564A1 METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED MEMORY CELL BASED ON A PULSED READ CURRENT 有权
标题翻译：基于脉冲读取电流读取基于磁悬浮连接（MTJ）的存储单元的方法和系统
公开(公告)号：US20150206564A1
公开(公告)日：2015-07-23
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/16 , G11C5/12
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

6. 发明申请

US20070153610A1 Dynamic body bias with bias boost 审中-公开
标题翻译：具有偏压增强的动态身体偏倚
公开(公告)号：US20070153610A1
公开(公告)日：2007-07-05
申请号：US11323361
申请日：2005-12-29
申请人： Fatih Hamzaoglu , Kevin Zhang , Yih Wang
发明人： Fatih Hamzaoglu , Kevin Zhang , Yih Wang
IPC分类号： G11C5/14
CPC分类号： G11C5/146 , H03K19/0016
摘要： For one disclosed embodiment, circuitry may bias one or more wells of a substrate from a first state to a second state. Bias by the circuitry of one or more wells of the substrate to the second state may be boosted. Other embodiments are also disclosed.
摘要翻译：对于一个所公开的实施例，电路可以将衬底的一个或多个阱从第一状态偏置到第二状态。通过衬底的一个或多个孔的电路到第二状态的偏置可以被提升。还公开了其他实施例。

7. 发明授权

US08451670B2 Adaptive and dynamic stability enhancement for memories 有权
标题翻译：存储器的自适应和动态稳定性增强
公开(公告)号：US08451670B2
公开(公告)日：2013-05-28
申请号：US12888575
申请日：2010-09-23
申请人： Pramod Kolar , Fatih Hamzaoglu , Yih Wang , Eric A Karl , Yong-Gee Ng , Uddalak Bhattacharya , Kevin X. Zhang , Hyunwoo Nho
发明人： Pramod Kolar , Fatih Hamzaoglu , Yih Wang , Eric A Karl , Yong-Gee Ng , Uddalak Bhattacharya , Kevin X. Zhang , Hyunwoo Nho
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C11/41 , G11C29/028
摘要： Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal.
摘要翻译：描述了存储器的自适应和动态稳定性增强。在一个示例中，增强包括多个传感器，每个传感器各自位于多个存储器单元附近以提供传感器电压，控制器接收传感器电压并基于此提供控制信号;以及读/写辅助电路，耦合到控制器，用于响应于所述控制信号调整应用于对所述多个存储器单元的存储单元的读取和写入的参数。

8. 发明申请

US20060002177A1 Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength 有权
标题翻译：具有动态可变p沟道金属氧化物半导体（PMOS）强度的六晶体管（6T）静态随机存取存储器（SRAM）
公开(公告)号：US20060002177A1
公开(公告)日：2006-01-05
申请号：US10883609
申请日：2004-06-30
申请人： Bo Zheng , Kevin Zhang , Fatih Hamzaoglu , Yih Wang
发明人： Bo Zheng , Kevin Zhang , Fatih Hamzaoglu , Yih Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C11/412
摘要： In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).
摘要翻译：在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

9. 发明授权

US09330747B2 Non-volatile latch using spin-transfer torque memory device 有权
标题翻译：使用自旋转移转矩存储器件的非易失性锁存器
公开(公告)号：US09330747B2
公开(公告)日：2016-05-03
申请号：US13894266
申请日：2013-05-14
申请人： Yih Wang , Fatih Hamzaoglu
发明人： Yih Wang , Fatih Hamzaoglu
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/1697 , G11C14/0081
摘要： Described is an apparatus of a non-volatile logic (NVL), the apparatus comprises: a sensing circuit to sense differential resistance; a first magnetic-tunneling-junction (MTJ) device coupled to the sensing circuit; a second MTJ device coupled to the sensing circuit, the first and second MTJ devices operable to provide differential resistance; and a buffer to drive complementary signals to the first and second MTJ devices respectively.
摘要翻译：描述了非易失性逻辑（NVL）的装置，该装置包括：用于感测差分电阻的感测电路; 耦合到感测电路的第一磁隧道结（MTJ）装置; 耦合到所述感测电路的第二MTJ装置，所述第一和第二MTJ装置可操作以提供差分电阻; 以及用于分别驱动与第一和第二MTJ装置的互补信号的缓冲器。

10. 发明申请

US20150117095A1 LOW RESISTANCE BITLINE AND SOURCELINE APPARATUS FOR IMPROVING READ AND WRITE OPERATIONS OF A NONVOLATILE MEMORY 有权
标题翻译：用于改善非易失性存储器的读取和写入操作的低电阻位线和电源设备
公开(公告)号：US20150117095A1
公开(公告)日：2015-04-30
申请号：US14129506
申请日：2013-10-31
申请人： Cyrille Dray , Blake C. Lin , Fatih Hamzaoglu , Liqiong Wei , Yih Wang
发明人： Cyrille Dray , Blake C. Lin , Fatih Hamzaoglu , Liqiong Wei , Yih Wang
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G06F3/0604 , G06F3/0659 , G06F3/067 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1697
摘要： Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.
摘要翻译：描述了一种用于提高读写余量的装置。该装置包括：源线; 第一个位线一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。还描述了一种装置，其包括：源线; 有位一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

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