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1. 发明申请

US20140003181A1 MEMORY CELL WITH IMPROVED WRITE MARGIN 有权
标题翻译：具有改进的写字符的存储单元
公开(公告)号：US20140003181A1
公开(公告)日：2014-01-02
申请号：US13997633
申请日：2012-03-30
申请人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
发明人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
IPC分类号： G11C5/14
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

2. 发明授权

US09111600B2 Memory cell with improved write margin 有权
标题翻译：具有改善写入容限的存储单元
公开(公告)号：US09111600B2
公开(公告)日：2015-08-18
申请号：US13997633
申请日：2012-03-30
申请人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
发明人： Yih Wang , Muhammad M. Khellah , Fatih Hamzaoglu
IPC分类号： G11C7/00 , G11C5/14 , G11C11/413
CPC分类号： G11C11/419 , G11C5/14 , G11C5/147 , G11C5/148 , G11C11/4074 , G11C11/412 , G11C11/413 , G11C11/417
摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.
摘要翻译：描述了一种用于改善存储器单元中的写入裕度的装置和系统。在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段的脉冲信号。在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

3. 发明授权

US07403426B2 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US07403426B2
公开(公告)日：2008-07-22
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Sung Kim , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , Bo Zheng
IPC分类号： G11C11/34
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

4. 发明申请

US20170277628A1 TECHNOLOGIES FOR MEMORY MANAGEMENT OF NEURAL NETWORKS WITH SPARSE CONNECTIVITY 审中-公开
公开(公告)号：US20170277628A1
公开(公告)日：2017-09-28
申请号：US15080144
申请日：2016-03-24
申请人： Somnath Paul , Charles Augustine , Muhammad M. Khellah , Sadique Ul Ameen Sheik
发明人： Somnath Paul , Charles Augustine , Muhammad M. Khellah , Sadique Ul Ameen Sheik
IPC分类号： G06F12/02 , G06N3/063
CPC分类号： G06N3/063 , G06N3/049
摘要： Technologies for memory management of a neural network include a compute device to read a memory of the compute device to access connectivity data associated with a neuron of the neural network, determine a memory address at which weights corresponding with the one or more network connections are stored, and access the corresponding weights from a memory location corresponding with the memory address. The connectivity data is indicative of one or more network connections from the neuron.

5. 发明申请

US20150009751A1 METHODS AND SYSTEMS TO SELECTIVELY BOOST AN OPERATING VOLTAGE OF, AND CONTROLS TO AN 8T BIT-CELL ARRAY AND/OR OTHER LOGIC BLOCKS 有权
标题翻译：选择性地增加对8T位单元阵列和/或其他逻辑块的操作电压和控制的方法和系统
公开(公告)号：US20150009751A1
公开(公告)日：2015-01-08
申请号：US14350546
申请日：2012-03-26
申请人： Jaydeep P. Kulkarni , Bibiche M. Geuskens , James Tschanz , Vivek K. De , Muhammad M. Khellah
发明人： Jaydeep P. Kulkarni , Bibiche M. Geuskens , James Tschanz , Vivek K. De , Muhammad M. Khellah
IPC分类号： G11C5/14 , G11C7/12 , G11C11/418 , G11C8/10 , G11C11/419
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译：提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。可以在读取模式期间升高单元Vcc，和/或写入字线（WWL）和/或读取字线（RWL）可以通过升压来断言。字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平转换器的延迟来延迟保持器控制的逻辑，以减少在初始NAND评估阶段。

6. 发明申请

US20140277812A1 DUAL LOOP DIGITAL LOW DROP REGULATOR AND CURRENT SHARING CONTROL APPARATUS FOR DISTRIBUTABLE VOLTAGE REGULATORS 审中-公开
标题翻译：双环数字低电平调节器和分布式电压调节器的电流共享控制装置
公开(公告)号：US20140277812A1
公开(公告)日：2014-09-18
申请号：US13801777
申请日：2013-03-13
申请人： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
发明人： Yi-Chun Shih , Kaushik Mazumdar , Stephen T. Kim , Rinkle Jain , James W. Tschanz , Muhammad M. Khellah
IPC分类号： G05F5/00
CPC分类号： G05F1/563 , G05F1/00 , G05F1/46 , H02M3/156
摘要： Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.
摘要翻译：描述了一种装置，其包括：耦合到输入电源和负载的多个晶体管; 第一比较器，其具有耦合到所述负载的第一节点，以及耦合到第一参考的第二节点; 第二比较器，其具有耦合到所述负载的第一节点，以及耦合到第二参考的第二节点，所述第二参考与所述第一参考不同; 以及逻辑单元，用于接收第一比较器的输出和第二比较器的输出，逻辑单元根据第一和第二比较器的输出接通或关断多个晶体管的晶体管。

7. 发明授权

US08762821B2 Method of correcting adjacent errors by using BCH-based error correction coding 有权
标题翻译：通过使用基于BCH的纠错编码校正相邻误差的方法
公开(公告)号：US08762821B2
公开(公告)日：2014-06-24
申请号：US13435152
申请日：2012-03-30
申请人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
发明人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1064 , H03M13/152 , H03M13/1575
摘要： An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depending on error type (either random error or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.
摘要翻译：提供了一种包括处理器的装置。处理器包括用于存储数据的缓存，解码器，错误分类模块和纠错模块。高速缓存存储数据，数据被编码为码字。解码器从缓存器读取码字，并使用H矩阵计算码字的校正子。错误分类模块确定综合征的错误类型。 H矩阵被重新设计，使得列形成几何序列，结果不仅可以校正t位随机误差，而且可以校正（t + 1）位相邻误差。由增强的误差分类模块触发的误差校正模块根据误差类型（随机误差或相邻误差）采用两组输入中的一组，并且当综合征包括可检测和可校正的误差时，产生校正数据。

8. 发明申请

US20130262957A1 Method Of Correcting Adjacent Errors By Using BCH-Based Error Correction Coding 有权
标题翻译：通过使用基于BCH的纠错编码校正相邻错误的方法
公开(公告)号：US20130262957A1
公开(公告)日：2013-10-03
申请号：US13435152
申请日：2012-03-30
申请人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
发明人： Wei Wu , Shih-Lien L. Lu , Muhammad M. Khellah
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G06F11/1064 , H03M13/152 , H03M13/1575
摘要： An apparatus is provided that comprises a processor. The processor comprises a cache to store data, a decoder, an error classification module, and an error correction module. The cache stores data, the data encoded as a codeword. The decoder reads the codeword from cache and calculates a syndrome of the codeword using an H-matrix. The error classification module determines an error type of the syndrome. The H-matrix is redesigned such that the columns form a geometrical sequence, and as a result not only the t-bit random errors but also (t+1) bit adjacent errors can be corrected. The error correction module, triggered by the enhanced error classification module, takes one of two sets of inputs depends on the error type (either random or adjacent error) and produces corrected data from the syndrome when the syndrome comprises a detectable and correctable error.
摘要翻译：提供了一种包括处理器的装置。处理器包括用于存储数据的缓存，解码器，错误分类模块和纠错模块。高速缓存存储数据，数据被编码为码字。解码器从缓存器读取码字，并使用H矩阵计算码字的校正子。错误分类模块确定综合征的错误类型。 H矩阵被重新设计，使得列形成几何序列，结果不仅可以校正t位随机误差，而且（t + 1）位相邻误差。由增强的误差分类模块触发的误差校正模块根据误差类型（随机或相邻误差）采用两组输入中的一组，并且当综合征包括可检测和可校正的误差时，产生校正数据。

9. 发明授权

US07817068B2 Low power serial link bus architecture 有权
标题翻译：低功率串行总线架构
公开(公告)号：US07817068B2
公开(公告)日：2010-10-19
申请号：US11428247
申请日：2006-06-30
申请人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
发明人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03M5/00
CPC分类号： H04L25/45
摘要： Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种利用多泵浦串行链路的总线架构，以及将编码和序列化到两个数据流的组合，以通过总线发送和接收串行数据流。编码和序列化的顺序取决于两个数据流的预期活动因素，并且被选择以减少平均能量耗散。描述和要求保护其他实施例。

10. 发明申请

US20080001793A1 LOW POWER SERIAL LINK BUS ARCHITECTURE 有权
标题翻译：低功率串行总线架构
公开(公告)号：US20080001793A1
公开(公告)日：2008-01-03
申请号：US11428247
申请日：2006-06-30
申请人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
发明人： Maged Ghoneima , Muhammad M. Khellah , Vivek K. De
IPC分类号： H03M9/00
CPC分类号： H04L25/45
摘要： Embodiments of the present invention provide a bus architecture utilizing multiple-pumped serial links, and a combination of encoding and serialization to two data streams to transmit and receive a serialized data stream over a bus. The order in which encoding and serialization takes place depends upon the anticipated activity factors of the two data streams, and is chosen to reduce average energy dissipation. Other embodiments are described and claimed.
摘要翻译：本发明的实施例提供一种利用多泵浦串行链路的总线架构，以及将编码和序列化到两个数据流的组合，以通过总线发送和接收串行数据流。编码和序列化的顺序取决于两个数据流的预期活动因素，并且被选择以减少平均能量耗散。描述和要求保护其他实施例。

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