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1. 发明授权

US09368204B2 Volatile/non-volatile memory cell 有权
标题翻译：易挥发/非易失性存储单元
公开(公告)号：US09368204B2
公开(公告)日：2016-06-14
申请号：US13980559
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
发明人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
IPC分类号： G11C11/00 , G11C13/00 , G11C11/15 , G11C11/16 , G11C11/412 , H03K19/0175
CPC分类号： G11C13/0069 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C14/0081 , G11C14/009 , H03K19/017581
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和被编程为具有第一电阻的第一电阻开关元件（202）之间的第一晶体管（102）以及耦合在被编程为具有第二电阻的第二存储节点（108）和第二电阻开关元件（204）之间的第二晶体管（104），所述第一晶体管的控制端耦合到所述第二存储节点，以及控制所述第二晶体管的端子耦合到所述第一存储节点; 以及适于通过将所述第一和第二存储节点耦合到第一电源电压（VDD，GND）来在所述第一和第二存储节点处存储数据值（DNV）的控制电路（602），所述数据值由相对电阻的第一和第二电阻开关元件。

2. 发明申请

US20140070844A1 VOLATILE/NON-VOLATILE MEMORY CELL 有权
标题翻译：挥发性/非易失性记忆细胞
公开(公告)号：US20140070844A1
公开(公告)日：2014-03-13
申请号：US13980559
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
发明人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
IPC分类号： G11C13/00 , H03K19/0175
CPC分类号： G11C13/0069 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C14/0081 , G11C14/009 , H03K19/017581
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和被编程为具有第一电阻的第一电阻开关元件（202）之间的第一晶体管（102）以及耦合在被编程为具有第二电阻的第二存储节点（108）和第二电阻开关元件（204）之间的第二晶体管（104），所述第一晶体管的控制端耦合到所述第二存储节点，以及控制所述第二晶体管的端子耦合到所述第一存储节点; 以及适于通过将所述第一和第二存储节点耦合到第一电源电压（VDD，GND）来在所述第一和第二存储节点处存储数据值（DNV）的控制电路（602），所述数据值由相对电阻的第一和第二电阻开关元件。

3. 发明申请

US20140078810A1 LOADLESS VOLATILE/NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：无负载/非易失性存储器单元
公开(公告)号：US20140078810A1
公开(公告)日：2014-03-20
申请号：US13980555
申请日：2012-01-19
申请人： Guillaume Prenat , Gregory Di Pendina , Kholdoun Torki
发明人： Guillaume Prenat , Gregory Di Pendina , Kholdoun Torki
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C14/0081 , G11C14/009
摘要： The invention concerns a memory device comprising at least one memory cell comprising: first and second transistors (102, 104) coupled between first and second storage nodes (106, 108) respectively and a first supply voltage, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; first and second resistance switching elements (202, 204) coupled in series with said first and second transistors respectively; and control circuitry (308) adapted to apply, during a programming phase of the first resistance switching element, a second supply voltage to said second storage node to active said first transistor, and then to apply said second supply voltage to said first storage node to generate a first write current (IA) through said first transistor and said first resistance switching element.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：分别耦合在第一和第二存储节点（106,108）之间的第一和第二晶体管（102,104）和第一电源电压，所述第一晶体管的控制端为耦合到所述第二存储节点，并且所述第二晶体管的控制端耦合到所述第一存储节点; 分别与所述第一和第二晶体管串联耦合的第一和第二电阻开关元件（202,204）以及适于在所述第一电阻切换元件的编程阶段期间将第二电源电压施加到所述第二存储节点以激活所述第一晶体管的控制电路（308），然后将所述第二电源电压施加到所述第一存储节点通过所述第一晶体管和所述第一电阻开关元件产生第一写入电流（IA）。

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