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1. 发明申请

US20140167816A1 MEMORY CELL WITH VOLATILE AND NON-VOLATILE STORAGE 有权
标题翻译：具有挥发性和非挥发性储存的记忆体
公开(公告)号：US20140167816A1
公开(公告)日：2014-06-19
申请号：US14126051
申请日：2012-06-14
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C13/00 , H03K19/177
CPC分类号： G11C13/0002 , G11C11/161 , G11C13/0028 , G11C14/00 , G11C14/0054 , G11C14/0081 , H03K19/177
摘要： The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：第一和第二对交叉耦合晶体管; 以及耦合在所述第一对晶体管的第一电源电压（VDD，GND）和第一晶体管之间并被编程为具有第一和第二电阻之一的第一电阻切换元件（202）以及控制电路，其适于通过将所述第一存储节点耦合到所述第二电源电压（VDD，GND）来存储在所述第一和第二存储节点处的数据值（DNV），所述数据值由所述第一电阻切换的编程电阻元件。

2. 发明授权

US09224463B2 Compact volatile/non-volatile memory cell 有权
标题翻译：紧凑型易失性/非易失性存储单元
公开(公告)号：US09224463B2
公开(公告)日：2015-12-29
申请号：US13980529
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C13/00 , G11C11/15 , G11C11/16 , H03K19/177 , G11C11/412
CPC分类号： G11C13/003 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C13/0069 , G11C14/0081 , G11C14/009 , H03K19/1776
摘要： A memory device includes at least one memory cell having a first transistor coupled between a first storage node and a first supply voltage; a second transistor coupled between a second storage node and the first supply voltage and a single resistance switching element. Control terminals of the first and second transistors are coupled to the second and first storage nodes respectively. The single resistive switching element is coupled in series with the first transistor and is programmable to have one of first and second resistances. The first storage node is coupled to a first access line via a third transistor connected to said first storage node, and the second storage node is coupled to a second access line via a fourth transistor connected to the second storage node.
摘要翻译：存储器件包括至少一个具有耦合在第一存储节点和第一电源电压之间的第一晶体管的存储单元; 耦合在第二存储节点和第一电源电压之间的第二晶体管和单个电阻开关元件。第一和第二晶体管的控制端分别耦合到第二和第一存储节点。单电阻开关元件与第一晶体管串联耦合，并且可编程为具有第一和第二电阻之一。第一存储节点经由连接到所述第一存储节点的第三晶体管耦合到第一存取线，并且第二存储节点经由连接到第二存储节点的第四晶体管耦合到第二存取线。

3. 发明授权

US09053782B2 Memory cell with volatile and non-volatile storage 有权
标题翻译：具有易失性和非易失性存储的存储单元
公开(公告)号：US09053782B2
公开(公告)日：2015-06-09
申请号：US14126051
申请日：2012-06-14
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C7/00 , G11C13/00 , G11C14/00 , G11C11/16 , H03K19/177
CPC分类号： G11C13/0002 , G11C11/161 , G11C13/0028 , G11C14/00 , G11C14/0054 , G11C14/0081 , H03K19/177
摘要： The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element (202) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (DNV) at said first and second storage nodes by coupling said first storage node to said second supply voltage (VDD, GND), the data value being determined by the programmed resistance of the first resistance switching element.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：第一和第二对交叉耦合晶体管; 以及耦合在所述第一对晶体管的第一电源电压（VDD，GND）和第一晶体管之间并被编程为具有第一和第二电阻之一的第一电阻切换元件（202）以及控制电路，其适于通过将所述第一存储节点耦合到所述第二电源电压（VDD，GND）来存储在所述第一和第二存储节点处的数据值（DNV），所述数据值由所述第一电阻切换的编程电阻元件。

4. 发明授权

US09368204B2 Volatile/non-volatile memory cell 有权
标题翻译：易挥发/非易失性存储单元
公开(公告)号：US09368204B2
公开(公告)日：2016-06-14
申请号：US13980559
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
发明人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
IPC分类号： G11C11/00 , G11C13/00 , G11C11/15 , G11C11/16 , G11C11/412 , H03K19/0175
CPC分类号： G11C13/0069 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C14/0081 , G11C14/009 , H03K19/017581
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和被编程为具有第一电阻的第一电阻开关元件（202）之间的第一晶体管（102）以及耦合在被编程为具有第二电阻的第二存储节点（108）和第二电阻开关元件（204）之间的第二晶体管（104），所述第一晶体管的控制端耦合到所述第二存储节点，以及控制所述第二晶体管的端子耦合到所述第一存储节点; 以及适于通过将所述第一和第二存储节点耦合到第一电源电压（VDD，GND）来在所述第一和第二存储节点处存储数据值（DNV）的控制电路（602），所述数据值由相对电阻的第一和第二电阻开关元件。

5. 发明授权

US09117521B2 Memory cell with volatile and non-volatile storage 有权
标题翻译：具有易失性和非易失性存储的存储单元
公开(公告)号：US09117521B2
公开(公告)日：2015-08-25
申请号：US14126067
申请日：2012-06-14
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C14/00
CPC分类号： G11C13/0069 , G11C7/106 , G11C11/161 , G11C13/0002 , G11C14/0081 , G11C14/009
摘要： The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.
摘要翻译：本发明涉及一种非易失性存储元件，包括：第一和第二晶体管（106,108），形成耦合在存储元件的第一存储节点（112）和输出（110）之间的反相器（104）耦合在所述第一存储节点（112）和第一电源电压（GND，VDD）之间并包括耦合到所述输出的控制端的第三晶体管（116）与所述第三晶体管串联耦合的第一电阻开关元件（102），并被编程为具有表示非易失性数据位的第一和第二电阻（Rmin，Rmax）之一; 耦合在所述存储节点（112）之间的第二电源电压（VDD，GND）的第四晶体管（118）以及控制电路（130），适于在所述非易失性数据位的传送阶段开始时激活所述第三晶体管到所述存储节点，并且在所述传输期间控制所述第四晶体管将所述存储节点耦合到所述第二电源电压相。

6. 发明授权

US09042157B2 Programmable volatile/non-volatile memory cell 有权
标题翻译：可编程易失性/非易失性存储单元
公开(公告)号：US09042157B2
公开(公告)日：2015-05-26
申请号：US13980558
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C13/00 , G11C11/16 , G11C11/412
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C13/0028 , G11C14/0081 , G11C14/009
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和第一电源线（GND，VDD）之间的第一晶体管（102）耦合在第二存储节点和所述第一电源线（GND，VDD）之间的第二晶体管（104），所述第一和第二晶体管的控制端分别耦合到所述第二和第一存储节点; 耦合在所述第一存储节点和第一接入线路（BL）之间并通过第一控制线路（WL1）可控的第三晶体管; 耦合在所述第二存储节点（108）和第二接入线（BLB）之间并经由第二控制线可控的第四晶体管（112,712）; 以及与所述第一晶体管串联耦合的第一电阻开关元件（202），并且可编程为具有第一和第二电阻状态之一。

7. 发明申请

US20140269003A1 MEMORY CELL WITH VOLATILE AND NON-VOLATILE STORAGE 有权
标题翻译：具有挥发性和非挥发性储存的记忆体
公开(公告)号：US20140269003A1
公开(公告)日：2014-09-18
申请号：US14126067
申请日：2012-06-14
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C7/106 , G11C11/161 , G11C13/0002 , G11C14/0081 , G11C14/009
摘要： The invention concerns a non-volatile memory element comprising: first and second transistors (106, 108) forming an inverter (104) coupled between a first storage node (112) and an output (110) of the memory element; a third transistor (116) coupled between the first storage node (112) and a first supply voltage (GND, VDD) and comprising a control terminal coupled to said output; a first resistance switching element (102) coupled in series with said third transistor and programmed to have one of first and second resistances (Rmin, Rmax) representing a non-volatile data bit; a fourth transistor (118) coupled between said storage node (112) a second supply voltage (VDD, GND); and control circuitry (130) adapted to activate said third transistor at the start of a transfer phase of said non-volatile data bit to said storage node, and to control said fourth transistor to couple said storage node to said second supply voltage during said transfer phase.
摘要翻译：本发明涉及一种非易失性存储元件，包括：第一和第二晶体管（106,108），形成耦合在存储元件的第一存储节点（112）和输出（110）之间的反相器（104）耦合在所述第一存储节点（112）和第一电源电压（GND，VDD）之间并包括耦合到所述输出的控制端的第三晶体管（116）与所述第三晶体管串联耦合的第一电阻开关元件（102），并被编程为具有表示非易失性数据位的第一和第二电阻（Rmin，Rmax）之一; 耦合在所述存储节点（112）之间的第二电源电压（VDD，GND）的第四晶体管（118）以及控制电路（130），适于在所述非易失性数据位的传送阶段开始时激活所述第三晶体管到所述存储节点，并且在所述传输期间控制所述第四晶体管将所述存储节点耦合到所述第二电源电压相。

8. 发明申请

US20140050012A1 PROGRAMMABLE VOLATILE/NON-VOLATILE MEMORY CELL 有权
标题翻译：可编程易失性/非易失性存储单元
公开(公告)号：US20140050012A1
公开(公告)日：2014-02-20
申请号：US13980558
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C13/0028 , G11C14/0081 , G11C14/009
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BL) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和第一电源线（GND，VDD）之间的第一晶体管（102）耦合在第二存储节点和所述第一电源线（GND，VDD）之间的第二晶体管（104），所述第一和第二晶体管的控制端分别耦合到所述第二和第一存储节点; 耦合在所述第一存储节点和第一接入线路（BL）之间并通过第一控制线路（WL1）可控的第三晶体管; 耦合在所述第二存储节点（108）和第二接入线（BLB）之间并经由第二控制线可控的第四晶体管（112,712）; 以及与所述第一晶体管串联耦合的第一电阻开关元件（202），并且可编程为具有第一和第二电阻状态之一。

9. 发明申请

US20140070844A1 VOLATILE/NON-VOLATILE MEMORY CELL 有权
标题翻译：挥发性/非易失性记忆细胞
公开(公告)号：US20140070844A1
公开(公告)日：2014-03-13
申请号：US13980559
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
发明人： Yoann Guillemenet , Lionel Torres , Guillaume Prenat , Kholdoun Torki , Gregory Di Pendina
IPC分类号： G11C13/00 , H03K19/0175
CPC分类号： G11C13/0069 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C14/0081 , G11C14/009 , H03K19/017581
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first resistance switching element (202) programmed to have a first resistance; and a second transistor (104) coupled between a second storage node (108) and a second resistance switching element (204) programmed to have a second resistance, a control terminal of said first transistor being coupled to said second storage node, and a control terminal of said second transistor being coupled to said first storage node; and control circuitry (602) adapted to store a data value (DNV) at said first and second storage nodes by coupling said first and second storage nodes to a first supply voltage (VDD, GND), the data value being determined by the relative resistances of the first and second resistance switching elements.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和被编程为具有第一电阻的第一电阻开关元件（202）之间的第一晶体管（102）以及耦合在被编程为具有第二电阻的第二存储节点（108）和第二电阻开关元件（204）之间的第二晶体管（104），所述第一晶体管的控制端耦合到所述第二存储节点，以及控制所述第二晶体管的端子耦合到所述第一存储节点; 以及适于通过将所述第一和第二存储节点耦合到第一电源电压（VDD，GND）来在所述第一和第二存储节点处存储数据值（DNV）的控制电路（602），所述数据值由相对电阻的第一和第二电阻开关元件。

10. 发明申请

US20140043062A1 COMPACT VOLATILE/NON-VOLATILE MEMORY CELL 有权
标题翻译：紧急挥发性/非易失性记忆细胞
公开(公告)号：US20140043062A1
公开(公告)日：2014-02-13
申请号：US13980529
申请日：2012-01-19
申请人： Yoann Guillemenet , Lionel Torres
发明人： Yoann Guillemenet , Lionel Torres
IPC分类号： G11C13/00 , H03K19/177
CPC分类号： G11C13/003 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/1675 , G11C11/1693 , G11C11/412 , G11C13/0002 , G11C13/0069 , G11C14/0081 , G11C14/009 , H03K19/1776
摘要： The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply voltage (GND, VDD); a second transistor (104) coupled between a second storage node (108) and said first supply voltage, control terminals of the first and second transistors being coupled to the second and first storage nodes respectively; and a single resistance switching element (202), wherein said single resistive switching element is coupled in series with said first transistor and is programmable to have one of first and second resistances (Rmin, Rmax), wherein said first storage node is coupled to a first access line (BL) via a third transistor (110, 810) connected to said first storage node, and said second storage node is coupled to a second access line (BLB) via a fourth transistor (112, 812) connected to said second storage node.
摘要翻译：本发明涉及一种包括至少一个存储单元的存储器件，包括：耦合在第一存储节点（106）和第一电源电压（GND，VDD）之间的第一晶体管（102）耦合在第二存储节点（108）和所述第一电源电压之间的第二晶体管（104），所述第一和第二晶体管的控制端分别耦合到所述第二和第一存储节点; 和单电阻开关元件（202），其中所述单电阻开关元件与所述第一晶体管串联耦合，并且可编程为具有第一和第二电阻（Rmin，Rmax）中的一个，其中所述第一存储节点耦合到第一接入线路（BL）经由连接到所述第一存储节点的第三晶体管（110,810），并且所述第二存储节点经由连接到所述第二存储节点的第四晶体管（112,812）耦合到第二存取线路（BLB）存储节点。

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