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    • 1. 发明授权
    • ATM cell/packet switch and communication control method using the same
    • ATM信元/分组交换和通信控制方法使用相同
    • US07304989B2
    • 2007-12-04
    • US10165682
    • 2002-06-07
    • Yuichi Tazaki
    • Yuichi Tazaki
    • H04L12/57
    • H04L12/5601H04L49/108H04L49/255H04L2012/5681
    • In order to provide an ATM cell/packet switch which can easily maintain the band for the normality confirmation packet of the user data transfer path without influencing the user band at a state of in-band, and a communication control method using the switch, at least provided in the switch are: an SDRAM for storing the user data; a normality confirmation packet generator; a timing generator for generating the timing of a refresh cycle of the SDRAM; a selector for transferring the normality confirmation packet at the time of the refresh; and a packet reception unit for extracting the packet identifying information from the received packet data, and comparing the normality confirmation packet directly received from the packet generator to the normality confirmation packet received via the switch unit thereby to confirm the normality when the packet data is the normality confirmation packet.
    • 为了提供能够容易地维持用户数据传输路径的正常确认分组的频带而不影响带内状态的用户频带的ATM信元/分组交换机,以及使用该交换机的通信控制方法 交换机中最少提供的是:用于存储用户数据的SDRAM; 正常确认包发生器; 定时发生器,用于产生SDRAM的刷新周期的定时; 用于在刷新时传送正常确认包的选择器; 以及分组接收单元,用于从接收到的分组数据中提取分组识别信息,并将从分组发生器直接接收的正常确认分组与经由切换单元接收到的正常确认分组进行比较,从而当分组数据为 正常确认包。
    • 4. 发明授权
    • Circuit emulation method and device
    • 电路仿真方法及装置
    • US08588219B2
    • 2013-11-19
    • US12820653
    • 2010-06-22
    • Yuichi Tazaki
    • Yuichi Tazaki
    • H04J1/02
    • H04L61/106
    • A circuit emulation method and device are provided that can enhance the efficiency in packet transmission and achieve the effective use of the network band by reducing the number of packets. A circuit emulation device for connecting a plurality of TDM circuits to an asynchronous network includes: a table storing the addresses of other circuit emulation devices on the asynchronous network, the addresses serving as the destinations for the plurality of TDM circuits; a packet assembly section that generates a multiplex packet in such a manner that a payload is made by bundling TDM data to those TDM circuits, among the plurality of TDM circuits, having the same destination address, which is found by referring to the table, and that the destination address is added to the payload; and a transmission section that transmits the multiplex packet to the asynchronous network.
    • 提供一种电路仿真方法和装置,其可以提高分组传输的效率,并通过减少分组数量来实现网络频带的有效使用。 用于将多个TDM电路连接到异步网络的电路仿真装置包括:存储异步网络上的其他电路仿真装置的地址的表,用作多个TDM电路的目的地的地址; 分组组合部分,以通过参考该表找到具有相同目的地地址的多个TDM电路中的TDM电路与TDM电路捆绑TDM数据来生成多路复用分组;以及 目的地址被添加到有效载荷; 以及将所述复用分组发送到所述异步网络的发送部。
    • 5. 发明授权
    • Front end module assembly structure
    • 前端模块组装结构
    • US07188892B2
    • 2007-03-13
    • US11082910
    • 2005-03-18
    • Yuichi TazakiMasaki YoshimitsuSatoshi Shiga
    • Yuichi TazakiMasaki YoshimitsuSatoshi Shiga
    • B62D25/08
    • B62D65/16B62D25/084
    • A front end module assembly structure for a vehicle, including: a first bracket plate provided on either a front end module or a side member, which is provided with a through hole and a slit extending upward therefrom; a second bracket plate provided on the other of the front end module and the side member to be mated to the first bracket plate, which has an insertion hole formed thereon at a position corresponding to the slit of the first bracket plate; and a locator piece attached to the second bracket plate. The locator piece has a portion configured to be inserted into the slit from a position inside the through hole and held in the slit, and a bottom face configured to be set on a periphery of the insertion hole when the locator piece is inserted into the insertion hole.
    • 一种用于车辆的前端模块组件结构,包括:设置在前端模块或侧构件上的第一支架板,其具有通孔和从其向上延伸的狭缝; 设置在所述前端组件和与所述第一支架板配合的另一侧的第二支架板,所述第二支架板在与所述第一支架板的狭缝对应的位置处形成有插入孔; 以及附接到第二支架板的定位器片。 所述定位片具有从所述通孔内的位置插入所述狭缝的部分,并且保持在所述狭缝中,并且当所述定位片插入到所述插入部中时,所述底面被配置为设置在所述插入孔的周围 孔。
    • 6. 发明授权
    • ATM cell/packet switch and communication control method using the same
    • ATM信元/分组交换和通信控制方法使用相同
    • US07944825B2
    • 2011-05-17
    • US11797415
    • 2007-05-03
    • Yuichi Tazaki
    • Yuichi Tazaki
    • H04L12/26H04L12/28H04L12/56
    • H04L12/5601H04L49/108H04L49/255H04L2012/5681
    • In order to provide an ATM cell□packet switch which can easily maintain the band for the normality confirmation packet of the user data transfer path without influencing the user band at a state of in□band, and a communication control method using the switch, at least provided in the switch are: an SDRAM for storing the user data; a normality confirmation packet generator; a timing generator for generating the timing of a refresh cycle of the SDRAM; a selector for transferring the normality confirmation packet at the time of the refresh; and a packet reception unit for extracting the packet identifying information from the received packet data, and comparing the normality confirmation packet directly received from the packet generator to the normality confirmation packet received via the switch unit thereby to confirm the normality when the packet data is the normality confirmation packet.
    • 为了提供能够容易地维持用户数据传送路径的正常确认分组的频带的ATM信元的分组交换机,而不影响在□频带的状态下的用户频带,以及使用该交换机的通信控制方法 交换机中最少提供的是:用于存储用户数据的SDRAM; 正常确认包发生器; 定时发生器,用于产生SDRAM的刷新周期的定时; 用于在刷新时传送正常确认包的选择器; 以及分组接收单元,用于从接收到的分组数据中提取分组识别信息,并将从分组发生器直接接收的正常确认分组与经由切换单元接收到的正常确认分组进行比较,从而当分组数据为 正常确认包。
    • 8. 发明授权
    • Method of and apparatus for producing a grinder used for a grinding
machine and grinding-particles packing apparatus
    • 用于研磨机的研磨机的生产方法和设备以及研磨颗粒包装设备
    • US5312540A
    • 1994-05-17
    • US10880
    • 1993-01-29
    • Hidehiro KuronoKoji HatanakaYuichi Tazaki
    • Hidehiro KuronoKoji HatanakaYuichi Tazaki
    • C25D15/00C25D5/02
    • C25D15/00
    • Super-hard grinding particles are electrodeposited on a metallic grinder matrix having recessed portions defined in an outer peripheral surface thereof to thereby produce a desired grinder used for a grinding machine. The grinder matrix is disposed within a mesh-like grinding-particle holder provided in a plating tank. Further, the grinding particles are packed into the grinding-particles holder. The grinding particles held in contact with the recessed portions of the grinder matrix are bonded to the grinder matrix using a plating layer formed by electroplating. The grinder matrix is reversed upsidedown and holding the grinding particles in contact with the recessed portions of the reversed grinder matrix. The grinding particles are bonded again to the grinder matrix using a plating layer formed by electroplating.
    • 将超硬研磨颗粒电沉积在具有限定在其外周表面中的凹部的金属研磨机基体上,从而产生用于研磨机的所需研磨机。 研磨机基体设置在设置在电镀槽中的网状研磨颗粒保持架内。 此外,研磨颗粒被包装到研磨颗粒保持器中。 与研磨基体的凹部保持接触的研磨颗粒使用通过电镀形成的镀层结合到研磨基体。 研磨机基体反向颠倒并保持研磨颗粒与反转研磨机基体的凹陷部分接触。 研磨颗粒使用通过电镀形成的镀层再次结合到研磨基体。
    • 9. 发明申请
    • SIGNAL SELECTING CIRCUIT AND SIGNAL SELECTING METHOD
    • 信号选择电路和信号选择方法
    • US20130266053A1
    • 2013-10-10
    • US13991518
    • 2011-12-06
    • Yuichi Tazaki
    • Yuichi Tazaki
    • H04L7/00
    • H04L7/0037G06F1/04H04B1/74H04L7/0337
    • A signal selecting circuit according to the present invention includes an abnormality detection circuit that detects an abnormality of the signal input as the main signal in an input stage, a select circuit that selects and outputs the signal input as the main signal among the plurality of signals in the normal state, and when the abnormality detection circuit detects an abnormality of the signal input as the main signal, selects and outputs the signal input as the reserve signal, and a delay circuit that delays the signal input as the main signal by a delay time and outputs the delayed signal to the select circuit, the delay time being equal to or greater than a total time of a detection time in the abnormality detection circuit and a signal switching time in the select circuit.
    • 根据本发明的信号选择电路包括异常检测电路,其检测作为输入级中的主信号输入的信号的异常,选择并输出在多个信号中作为主信号输入的信号的选择电路 在正常状态下,当异常检测电路检测到作为主信号输入的信号的异常时,选择并输出输入的信号作为保留信号,延迟电路将输入的信号作为主信号延迟延迟 时间并将延迟的信号输出到选择电路,延迟时间等于或大于异常检测电路中的检测时间的总时间和选择电路中的信号切换时间。
    • 10. 发明申请
    • BUS CONTROL APPARATUS AND BUS CONTROL METHOD
    • 总线控制装置和总线控制方法
    • US20130067130A1
    • 2013-03-14
    • US13697977
    • 2011-05-16
    • Yuichi Tazaki
    • Yuichi Tazaki
    • G06F13/20
    • H04L12/4015G06F11/0745G06F11/0772G06F11/0781G06F11/0784G06F13/20G06F13/22G06F13/4282H04L41/06H04L69/40
    • An exemplary object is to make it possible to prompt notify a master-end control unit of failure information of a controlled device in a bus control apparatus that employs a structure in which a master-end circuit part is connected to a slave-end circuit part through a serial bus. A master circuit equipped with a control unit generates an access message for access to a control target equipped with a slave circuit, and transmits the access message to the slave circuit connected to the master circuit through a bus. The slave circuit collects information on the control target, generates a response message to the access message, generates an information message based on the information on the control target, and transmits the response message and the information message to the master circuit. If generation of the response message conflicts with generation of the information message, the slave circuit generates the information message, with a higher priority given to the generation of the information message.
    • 示例性的目的是使得可以在总线控制装置中提示通知主端控制单元的受控装置的故障信息,该总线控制装置采用将主端电路部分连接到从端电路部分的结构 通过串行总线。 配备有控制单元的主电路产生访问配备有从电路的控制对象的访问消息,并且通过总线将访问消息发送到与主电路连接的从电路。 从电路收集关于控制对象的信息,生成对接入消息的响应消息,根据控制对象的信息生成信息消息,并将响应消息和信息消息发送给主电路。 如果响应消息的产生与信息消息的产生冲突,则从电路产生信息消息,对信息消息的产生具有较高的优先级。