专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07844934B2 Method for designing a semiconductor integrated circuit layout capable of reducing the processing time for optical proximity effect correction 有权
标题翻译：用于设计能够减少光学邻近效应校正的处理时间的半导体集成电路布局的方法
公开(公告)号：US07844934B2
公开(公告)日：2010-11-30
申请号：US11486107
申请日：2006-07-14
申请人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
发明人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5072 , G06F17/5068
摘要： According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
摘要翻译：根据本发明，一种用于设计半导体集成电路布局的方法包括以下步骤：布置基本逻辑单元，其是与半导体集成电路的逻辑组件对应的电路图案; 布置基本逻辑单元之间的布线; 搜索没有布置基本逻辑单元的空白区域; 从空白区域提取矩形区域; 如果矩形区域大于指定尺寸，则根据预定规则将填充单元布置在矩形区域中，并根据预定规则将填充单元分组成伪层级单元以形成层次; 将填充单元布置在剩余的空白区域中; 以及对半导体集成电路图案执行光学邻近效应校正。

2. 发明申请

US20070124714A1 Method for designing semiconductor integrated circuit layout 有权
标题翻译：设计半导体集成电路布局的方法
公开(公告)号：US20070124714A1
公开(公告)日：2007-05-31
申请号：US11486107
申请日：2006-07-14
申请人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
发明人： Yusaku Ono , Osamu Suga , Kazuyuki Sakata , Hirofumi Taguchi , Yushi Okuno , Toshiaki Sugioka , Daisuke Kondo
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068
摘要： According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wiring between the basic logic cells; searching for a blank area in which none of the basic logic cells is arranged; extracting a rectangular region from the blank area; if the rectangular region is larger than a specified size, arranging fill cells in the rectangular region according to a predetermined rule and grouping the fill cells into pseudo-hierarchical cells according to a predetermined rule to form a hierarchy; arranging fill cells in the remaining blank areas; and performing optical proximity effect correction on the semiconductor integrated circuit pattern.
摘要翻译：根据本发明，一种用于设计半导体集成电路布局的方法包括以下步骤：布置基本逻辑单元，其是与半导体集成电路的逻辑组件对应的电路图案; 布置基本逻辑单元之间的布线; 搜索没有布置基本逻辑单元的空白区域; 从空白区域提取矩形区域; 如果矩形区域大于指定尺寸，则根据预定规则将填充单元布置在矩形区域中，并根据预定规则将填充单元分组成伪分层单元以形成层次; 将填充单元布置在剩余的空白区域中; 以及对半导体集成电路图案执行光学邻近效应校正。

3. 发明申请

US20080270089A1 Through-current power table, method of generating thereof and method of calculating power consumption 审中-公开
标题翻译：直流功率表，其产生方法和计算功耗的方法
公开(公告)号：US20080270089A1
公开(公告)日：2008-10-30
申请号：US12081057
申请日：2008-04-10
申请人： Yushi Okuno , Takashi Nakaya
发明人： Yushi Okuno , Takashi Nakaya
IPC分类号： G06F17/10 , G06F17/30
CPC分类号： G06F17/5036 , G06F2217/78
摘要： A through-current power table indicates through-current power of a standard cell with respect to each combination of plural kinds of waveform distortion of an input signal input to the standard cell and plural kinds of power supply voltage supplied to the standard cell. A method of calculating power consumption of a circuit comprises: performing a computer simulation of the circuit to calculate waveform distortion of an input signal with respect to each standard cell; calculating through-current power corresponding to the calculated waveform distortion and a specified power supply voltage by reference to the through-current power table; calculating charge-discharge power of the circuit by using load capacitance information of the circuit and the specified power supply voltage; and calculating power consumption of the circuit based on the calculated through-current power and the calculated charge-discharge power.
摘要翻译：通过电流表表示对于输入到标准单元的输入信号的多种波形失真和提供给标准单元的多种电源电压的各种组合，标准单元的通电功率。一种计算电路功耗的方法包括：对所述电路进行计算机模拟以计算输入信号相对于每个标准单元的波形失真; 通过参考电流功率表计算与计算出的波形失真相对应的通电功率和指定的电源电压; 通过使用电路的负载电容信息和指定的电源电压来计算电路的充放电功率; 以及基于所计算的通流功率和计算的充放电功率计算电路的功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式