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1. 发明申请

US20230123349A1 DUTY CYCLE CORRECTION CIRCUIT 有权
公开(公告)号：US20230123349A1
公开(公告)日：2023-04-20
申请号：US18068070
申请日：2022-12-19
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Yalan Lv , Xiangyang Guo , Ranran Feng
IPC分类号： H03K3/017
摘要： A duty cycle correction circuit includes a sawtooth wave generating unit, a voltage regulating unit, a differential comparator, a differential amplifier and low-pass filters. The sawtooth wave generating unit converts a narrow pulse signal into a sawtooth wave signal with a duty cycle of 50% which is input into the differential comparator. The voltage regulating unit regulates an input voltage value of a non-inverting input terminal of the differential comparator. The differential comparator compares a voltage difference between input signals of input terminals and outputs an output clock signal. The low-pass filters input DC components to the differential amplifier which amplifies the DC signals and output to the voltage regulating unit. The duty cycle correction circuit has a small chip occupying area to realize high integration of the chip, and the duty cycle of the output clock is accurately corrected to ensure the stability of the output clock frequency.

2. 发明授权

US09535449B2 Circuit for generating USB peripheral clock and method therefor 有权
标题翻译：用于生成USB外设时钟的电路及其方法
公开(公告)号：US09535449B2
公开(公告)日：2017-01-03
申请号：US14084467
申请日：2013-11-19
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Xiu Yang
IPC分类号： G06F1/00 , G06F1/04
CPC分类号： G06F1/04
摘要： A circuit for generating USB peripheral clock comprises: an internal oscillator, a controllable frequency divider, a frequency multiplier, a receiving counter and a frequency division controller, wherein the internal oscillator generates a clock having a fixed frequency; the controllable frequency divider processes frequency division on the clock generated by the internal oscillator; the frequency multiplier processes frequency multiplication on the clock after frequency division and transmits the clock after frequency multiplication to the USB main structure; the receiving counter receives an SOF packet which is transmitted by a host according to the clock outputted by the frequency multiplier, and counts intervals of receiving the SOF packet; and the frequency division controller compares the difference between the counting result of the receiving counter and a standard interval, controls and regulates frequency division parameters of the controllable frequency divider according to a comparing result thereof.
摘要翻译：一种用于产生USB外围时钟的电路包括：内部振荡器，可控分频器，倍频器，接收计数器和分频控制器，其中内部振荡器产生具有固定频率的时钟; 可控分频器对由内部振荡器产生的时钟进行分频; 倍频器在分频后对时钟进行倍频，并将倍频后的时钟发送到USB主机结构; 接收计数器接收根据由倍频器输出的时钟由主机发送的SOF分组，并计数接收该SOF分组的间隔; 并且分频控制器将接收计数器的计数结果与标准间隔之间的差进行比较，根据其比较结果来控制和调节可控分频器的分频参数。

3. 发明授权

US09252760B2 Signal amplitude detection circuit 有权
标题翻译：信号幅度检测电路
公开(公告)号：US09252760B2
公开(公告)日：2016-02-02
申请号：US14459285
申请日：2014-08-13
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Ziche Zhang , Zhengxian Zou
IPC分类号： H03D1/00 , H03K5/00 , H03K5/24
CPC分类号： H03K5/2409 , H03K5/2472
摘要： A signal amplitude detection circuit includes a detector and a trimming algorithm module, and the detector having a preset baseline threshold reference value and an output terminal connected with the trimming algorithm module which is arranged for recording and decoding an output result of the detector to output an amplitude code value, and generating a control signal for controlling the baseline threshold reference value rise to a power supply level from a ground level or drop to the ground level from the power supply level, and the output result of the detector being “1” if a crossover occurs between the baseline threshold reference value and the detected signal; otherwise being “0”. The signal amplitude detection circuit detects the signal amplitude in a digital way, which has simpler structure, lower power consumption, reduced size of chips, and stable and accurate detection result without PVT drift.
摘要翻译：信号幅度检测电路包括检测器和修整算法模块，检测器具有预设的基准阈值参考值，以及与修整算法模块连接的输出端子，该修整算法模块被布置用于记录和解码检测器的输出结果以输出并且产生用于控制基准阈值参考值的控制信号从地电平上升到电源电平或从电源电平下降到地电平，并且检测器的输出结果如果在基准阈值参考值和检测到的信号之间发生交叉; 否则为“0”。信号幅度检测电路以数字方式检测信号幅度，结构更简单，功耗更低，芯片尺寸减小，无PVT漂移的稳定准确的检测结果。

4. 发明授权

US09191242B2 Differential signal detecting device 有权
标题翻译：差分信号检测装置
公开(公告)号：US09191242B2
公开(公告)日：2015-11-17
申请号：US14070560
申请日：2013-11-03
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Fangping Fan
IPC分类号： H04L25/06 , H04L25/02
CPC分类号： H04L25/0272 , H04L25/0292
摘要： A differential signal detecting device includes a secondary amplifier; a front-end receiver and a final amplifier which are respectively connected to the secondary amplifier; and a signal outputter which is connected to the final amplifier. The front-end receiver receives two externally inputted channels of differential signals and an externally inputted reference threshold voltage, differentiates and transduces the two channels of differential signals. The secondary amplifier receives and amplifies the signals which are outputted by the front-end receiver, and outputs the signals amplified again. The final amplifier differentiates and amplifies the signals outputted by the secondary amplifier and outputs the two channels of differentiated signals. The signal outputter receives the two channels of differentiated signals which are outputted by the final amplifier and processes the two channels of differentiated signals with a logical conjunction before outputting.
摘要翻译：差分信号检测装置包括二次放大器; 分别连接到次级放大器的前端接收器和最终放大器; 以及连接到最终放大器的信号输出器。前端接收器接收两个外部输入的差分信号通道和外部输入的参考阈值电压，差分和转换差分信号的两个通道。次级放大器接收并放大由前端接收机输出的信号，并输出再次放大的信号。最终的放大器对由次级放大器输出的信号进行微分和放大，并输出两路微分信号。信号输出器接收由最终放大器输出的两路微分信号，并在输出之前用逻辑连接处理两路微分信号。

5. 发明授权

US08952733B2 Frequency multiplier circuit and system 有权
标题翻译：倍频电路和系统
公开(公告)号：US08952733B2
公开(公告)日：2015-02-10
申请号：US13951331
申请日：2013-07-25
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Fangping Fan
IPC分类号： H03B19/00 , H03B19/14
CPC分类号： H03B19/14
摘要： A frequency multiplier circuit includes a first signal input terminal, a second signal input terminal, an output terminal, a power source terminal, a ground terminal, a main control circuit which is connected to the first signal input terminal, the second signal input terminal, the power source terminal and the ground terminal, a reference circuit which is connected to the power source terminal and the ground terminal, and a frequency synthesis circuit which is connected to the main control circuit, the reference circuit, the output terminal, the power source terminal and the ground terminal.
摘要翻译：倍频电路包括第一信号输入端子，第二信号输入端子，输出端子，电源端子，接地端子，连接到第一信号输入端子的主控制电路，第二信号输入端子，电源端子和接地端子，连接到电源端子和接地端子的参考电路，以及连接到主控制电路，参考电路，输出端子，电源的频率合成电路端子和接地端子。

6. 发明申请

US20150030117A1 Shift frequency divider circuit 审中-公开
标题翻译：移位分频电路
公开(公告)号：US20150030117A1
公开(公告)日：2015-01-29
申请号：US14515388
申请日：2014-10-15
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Guo Zhang
IPC分类号： H03K21/40 , H03K21/38
CPC分类号： H03K21/40 , H03K21/38
摘要： A shift frequency divider circuit includes: an inverter; N−1 registers; and N−2 logic gates; wherein each reset terminal of the register is connected to a system reset signal terminal; an output terminal of the inverter is respectively connected to an input terminal of the No. 1 register and input terminals of all the logic gates; all the logic gates are respectively connected between output terminals and input terminals of the No. 1 register to the No. N−1 register, and the output terminal of the No. 1 register is connected to another input terminal of the No. 1 logic gate, an output terminal of the No. 1 logic gate is connected to the input terminal of the No. 2 register; an output terminal of the No. N−2 logic gate is connected to the input terminal of the No. N−1 register.
摘要翻译：移位分频电路包括：逆变器; N-1个寄存器; 和N-2个逻辑门; 其中寄存器的每个复位端连接到系统复位信号端; 反相器的输出端分别连接到1号寄存器的输入端和所有逻辑门的输入端; 所有逻辑门分别连接到No. 1寄存器的输出端子和输入端子到N-1寄存器，并且1号寄存器的输出端子连接到1号逻辑电路的另一个输入端子 1号逻辑门的输出端连接到2号寄存器的输入端; N-2逻辑门的输出端连接到N-1号寄存器的输入端。

7. 发明申请

US20140176240A1 High-frequency bandwidth amplifying circuit 审中-公开
标题翻译：高频带宽放大电路
公开(公告)号：US20140176240A1
公开(公告)日：2014-06-26
申请号：US14062742
申请日：2013-10-24
申请人： IPGoal Microelectronics (Sichuan) Co., Ltd.
发明人： Ziche Zhang
IPC分类号： H03F1/48 , H03F3/68 , H03F3/19
CPC分类号： H03F1/48 , H03F3/19 , H03F3/68
摘要： A high-frequency bandwidth amplifying circuit includes a forward channel and a backward channel. An input terminal of the forward channel and an external forward input terminal are connected; an output terminal of the forward channel and a forward output port are connected. An input terminal of the backward channel and an external backward input terminal are connected; an output terminal of the backward channel and a backward output port are connected. The high-frequency bandwidth amplifying circuit further includes a feedback network. The forward channel includes a first operational amplifier and a second operational amplifier. An input terminal of the first operational amplifier is connected to the external forward input terminal; an output terminal of the first operational amplifier is connected to an input terminal of the second operational amplifier; and an output terminal of the second operational amplifier is connected to the forward output port.
摘要翻译：高频带宽放大电路包括正向信道和反向信道。连接正向通道的输入端和外部正向输入端; 连接正向通道的输出端子和正向输出端口。连接反向通道的输入端子和外部反向输入端子; 反向通道的输出端子和反向输出端口被连接。高频带宽放大电路还包括反馈网络。前向通道包括第一运算放大器和第二运算放大器。第一运算放大器的输入端连接到外部正向输入端; 第一运算放大器的输出端连接到第二运算放大器的输入端; 并且第二运算放大器的输出端连接到正向输出端口。

8. 发明申请

US20140176204A1 Phase locked loop system and working method thereof 审中-公开
标题翻译：锁相环系统及其工作方法
公开(公告)号：US20140176204A1
公开(公告)日：2014-06-26
申请号：US14062772
申请日：2013-10-24
申请人： Fangping Fan
发明人： Fangping Fan
IPC分类号： H03L7/07
CPC分类号： H03L7/235
摘要： A PLL system includes: an input end; an output end; a first PFD; a first CHP connected to the first PFD; a first LPF connected to the first CHP; a first VCO connected to the first CHP and the first LPF; a second PFD connected to the first VCO; a second CHP connected to the second PFD; a second LPF connected to the second CHP; a second VCO connected to the second CHP and the second LPF; a first DIV connected to the first PFD and the second VCO; and a second DIV connected to the second PFD and the second VCO. A working method of the PLL system is also provided, which can restrain input noise as well as phase noise of the second VOC in such a manner that noise of the PLL system is well restrained.
摘要翻译： PLL系统包括：输入端; 输出端第一个PFD; 连接到第一PFD的第一个CHP; 连接到第一CHP的第一LPF; 连接到第一CHP和第一LPF的第一VCO; 连接到第一VCO的第二PFD; 连接到第二PFD的第二个CHP; 连接到第二CHP的第二LPF; 连接到第二CHP和第二LPF的第二VCO; 连接到第一PFD和第二VCO的第一DIV; 以及连接到第二PFD和第二VCO的第二DIV。还提供了一种PLL系统的工作方法，其可以以如下方式抑制第二VOC的输入噪声以及相位噪声，使PLL系统的噪声得到很好的抑制。

9. 发明申请

US20140086432A1 POP noise suppression circuit and system 审中-公开
标题翻译： POP噪声抑制电路和系统
公开(公告)号：US20140086432A1
公开(公告)日：2014-03-27
申请号：US13624825
申请日：2012-09-21
申请人： Baoding Yang
发明人： Baoding Yang
IPC分类号： H04B15/00
CPC分类号： H03F1/305 , H03F2200/03 , H03G3/348
摘要： A POP noise suppression circuit includes a power source terminal, a clock signal input terminal, a charge unit, a discharge unit, a common-mode voltage judging and switching control unit, a charge and discharge capacitor, and a ground terminal. The charge unit includes a first clock generation circuit for generating a first pair of non-overlapped clock signal, and a first equivalent resistor. The discharge unit includes a second clock generation circuit for generating a second pair of non overlapped clock signals, and a second equivalent resistor. The charge unit generates a charge voltage changing slowly to the charge and discharge capacitor. The discharge unit generates a discharge voltage changing slowly to the charge and discharge capacitor. A POP noise suppression system is further provided.
摘要翻译： POP噪声抑制电路包括电源端子，时钟信号输入端子，充电单元，放电单元，共模电压判定和开关控制单元，充放电电容器和接地端子。充电单元包括用于产生第一对非重叠时钟信号的第一时钟产生电路和第一等效电阻器。放电单元包括用于产生第二对非重叠时钟信号的第二时钟产生电路和第二等效电阻器。充电单元产生对充放电电容器缓慢变化的充电电压。放电单元产生缓慢地向充放电电容器变化的放电电压。还提供了一种POP噪声抑制系统。

10. 发明申请

US20130169334A1 INTERPOLATION CIRCUIT AND INTERPOLATION SYSTEM 有权
标题翻译：插值电路和插值系统
公开(公告)号：US20130169334A1
公开(公告)日：2013-07-04
申请号：US13626831
申请日：2012-09-25
申请人： Ziche Zhang
发明人： Ziche Zhang
IPC分类号： H03K5/135
CPC分类号： H03K5/135
摘要： An interpolation circuit, includes a bias generating module, a load module consisting of a current source sub-module and a load resistance sub-module, first and second clock control modules, and an output module. The first clock control module includes a first input sub-module, a first source terminal negative feedback sub-module, a first multiplex switch sub-module and a first multiplex current sink sub-module. The bias generating module includes first, second and third FETs, and a bias current terminal. The current source sub-module includes fourth and fifth FETs. The load resistance sub-module includes first and second resistors. The first input sub-module includes sixth and seventh FETs. The first source terminal negative feedback sub-module includes a third resistor and a first capacitor. The first multiplex switch sub-module includes first and second groups of switches. The first multiplex current sink sub-module includes first and second groups of FETs. An interpolation system is further provided.
摘要翻译：内插电路包括偏置生成模块，由电流源子模块和负载电阻子模块构成的负载模块，第一和第二时钟控制模块以及输出模块。第一时钟控制模块包括第一输入子模块，第一源极端子负反馈子模块，第一多路复用开关子模块和第一多路复用电流模块子模块。偏置产生模块包括第一，第二和第三FET以及偏置电流端子。电流源子模块包括第四和第五FET。负载电阻子模块包括第一和第二电阻器。第一输入子模块包括第六和第七FET。第一源极端子负反馈子模块包括第三电阻器和第一电容器。第一多路开关子模块包括第一和第二组开关。第一多路电流吸收子模块包括第一和第二组FET。还提供了一种插值系统。

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