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1. 发明授权

US09979408B2 Apparatus and methods for phase synchronization of phase-locked loops 有权
公开(公告)号：US09979408B2
公开(公告)日：2018-05-22
申请号：US15147408
申请日：2016-05-05
申请人： ANALOG DEVICES, INC.
发明人： Christopher Mayer , David J. McLaurin , Christopher W. Angell , Sudhir Desai , Steven R. Bal
IPC分类号： H03L7/091 , H03L7/093 , H04B7/0413 , H03L7/087 , H03L7/23 , H03L7/197 , H03L7/089 , H04L7/033
CPC分类号： H03L7/1976 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/093 , H03L7/23 , H03L7/235 , H04B7/0413 , H04L7/0331
摘要： Apparatus and methods for phase synchronization of phase-locked loops (PLLs) are provided. In certain configurations, an RF communication system includes a PLL that generates one or more output clock signals and a phase synchronization circuit that synchronizes a phase of the PLL. The phase synchronization circuit includes a sampling circuit that generates samples by sampling the one or more output clock signals based on timing of a reference clock signal. Additionally, the phase synchronization circuit includes a phase difference calculation circuit that generates a phase difference signal based on the samples and a tracking digital phase signal representing the phase of the PLL. The phase synchronization circuit further includes a phase adjustment control circuit that provides a phase adjustment to the PLL based on the phase difference signal so as to synchronize the PLL.

2. 发明申请

US20180138914A1 Low-Power Fractional-N PLLs 审中-公开
公开(公告)号：US20180138914A1
公开(公告)日：2018-05-17
申请号：US15612908
申请日：2017-06-02
申请人： Perceptia Devices, Inc.
发明人： André Grouwstra , Julian Jenkins
IPC分类号： H03L7/14 , H03L7/091 , H03L7/197
CPC分类号： H03L7/14 , H03L7/0802 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/0992 , H03L7/181 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control code that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. The PLL may be implemented with dedicated or off-the-shelf circuitry, in an FPGA, or with a programmable processor. A tangible non-transitory memory may hold an associated software instructions for fractional-N phase locking.

3. 发明申请

US20180138913A1 Fractional-N PLL with Sleep Modes 审中-公开
公开(公告)号：US20180138913A1
公开(公告)日：2018-05-17
申请号：US15795119
申请日：2017-10-26
申请人： Perceptia Devices, Inc.
发明人： André Grouwstra , Julian Jenkins
IPC分类号： H03L7/08 , H03L7/099 , H03L7/085 , H03L7/093
CPC分类号： H03L7/14 , H03L7/0802 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/0992 , H03L7/181 , H03L7/1976 , H03L7/235 , H03L2207/50
摘要： A phase-locked loop (PLL) has an oscillator, a counter and a register to sample the oscillator phase as an integer number. A phase predictor uses a fractional-N frequency control word (FCW) to calculate a predicted phase as an integer number. The integer difference between the sampled phase and the predicted phase is used as loop filter input, to generate an oscillator control signal that adjusts the oscillator frequency. The phase predictor may provide noise shaping, for example via a MASH modulator. A first sleep mode control signal blocks a reference clock and feedback of the oscillator clock to the counter. It may also freeze loop filter parameters and block the output clock. A second sleep mode control signal may stop the oscillator.

4. 发明授权

US09973196B2 Clock synchronizer 有权
公开(公告)号：US09973196B2
公开(公告)日：2018-05-15
申请号：US15085821
申请日：2016-03-30
申请人： NXP B.V.
发明人： Jos Verlinden , Remco van de Beek , Stefan Mendel
IPC分类号： H03L7/087 , H03L7/197 , H03L7/23 , H03L7/107 , H03L7/18 , H04B5/00 , H04L7/033 , H04W4/00
CPC分类号： H03L7/087 , H03L7/1075 , H03L7/1803 , H03L7/197 , H03L7/1974 , H03L7/235 , H04B5/0031 , H04L7/0331 , H04W4/80
摘要： Apparatus for clock synchronization comprising a first phase locked loop (405) and a second phase locked loop (400). The first phase locked loop (405) is configured to receive a reference signal (Fcrystal) having a reference frequency, and operable to produce an output signal (Fout) having an output frequency that is a multiple of the reference frequency. The first phase locked loop (405) comprises a frequency divider (428) that controls the multiple in response to a control signal. The second phase locked loop (400) is configured to determine a phase error between the output signal (Fout) and an input signal (Fantenna), and to provide the control signal to the first phase locked loop (405). The second phase locked loop (400) comprises phase adjustment means (450), operable to adjust a phase difference between the input and output signal by varying the control signal for a duration.

5. 发明申请

US20170373826A1 CLOCK SYNCHRONIZER AND METHOD OF ESTABLISHING AN OUTPUT CLOCK 审中-公开
公开(公告)号：US20170373826A1
公开(公告)日：2017-12-28
申请号：US15698465
申请日：2017-09-07
申请人： Christopher Julian Travis
发明人： Christopher Julian Travis
IPC分类号： H04L7/033 , H03L7/10 , H03L7/099 , H03L7/087 , H03L7/085 , H03L7/083 , H03L7/07 , H03K3/03 , H03L7/23 , G06F1/025
CPC分类号： H04L7/0331 , G06F1/025 , G06F2211/902 , H03K3/0307 , H03L7/07 , H03L7/083 , H03L7/085 , H03L7/087 , H03L7/0991 , H03L7/0994 , H03L7/0995 , H03L7/10 , H03L7/235
摘要： A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

6. 发明申请

US20170331483A1 Wide Range Frequency Synthesizer with Quadrature Generation and Spur Cancellation 审中-公开
公开(公告)号：US20170331483A1
公开(公告)日：2017-11-16
申请号：US15605932
申请日：2017-05-25
申请人： Rambus Inc.
发明人： Masum Hossain , Farshid Aryanfar
IPC分类号： H03L7/23 , H03L7/18 , H03L7/099 , H03L7/081 , H03L7/08
CPC分类号： H03L7/235 , H03L7/0805 , H03L7/081 , H03L7/099 , H03L7/0995 , H03L7/18 , H03L7/23
摘要： A frequency synthesizer generates a wide range of frequencies from a single oscillator while achieving good noise performance. A cascaded phase-locked loop (PLL) circuit includes a first PLL circuit with an LC voltage controlled oscillator (VCO) and a second PLL circuit with a ring VCO. A feedforward path from the first PLL circuit to the second PLL circuit provides means and signal path for cancellation of phase noise, thereby reducing or eliminating spur and quantization effects. The frequency synthesizer can directly generate in-phase and quadrature phase output signals. A split-tuned ring-based VCO is controlled via a phase error detection loop to reduce or eliminate phase error between the quadrature signals.

7. 发明申请

US20170134153A1 Clock and Data Recovery Having Shared Clock Generator 有权
公开(公告)号：US20170134153A1
公开(公告)日：2017-05-11
申请号：US15339342
申请日：2016-10-31
申请人： Rambus Inc.
发明人： Masum Hossain , Brian Leibowitz , Jihong Ren
IPC分类号： H04L7/00 , H04L27/32
CPC分类号： H04L7/0016 , H03L7/1974 , H03L7/235 , H04L7/033 , H04L27/0014 , H04L27/32 , H04L2027/0016 , H04L2027/0036 , H04L2027/0053 , H04L2027/0055 , H04L2027/0067
摘要： This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

8. 发明申请

US20160352504A1 BURST MODE CLOCK DATA RECOVERY DEVICE AND METHOD THEREOF 有权
标题翻译：冲击模式时钟数据恢复装置及其方法
公开(公告)号：US20160352504A1
公开(公告)日：2016-12-01
申请号：US15159146
申请日：2016-05-19
申请人： Realtek Semiconductor Corp.
发明人： LIJUN GU , MING LI , LING CHEN
IPC分类号： H04L7/00 , H04L7/033
CPC分类号： H04L7/0087 , H03L7/0807 , H03L7/081 , H03L7/087 , H03L7/091 , H03L7/10 , H03L7/1974 , H03L7/235 , H04L7/0004 , H04L7/0025 , H04L7/033
摘要： A burst mode clock data recovery device includes a clock data recovery loop, a frequency tracking loop, a frequency tracking loop, and a fast-locking unit. The clock data recovery loop receives a sampling clock signal and a data signal and uses the sampling clock signal to lock the data signal to generate a recovery clock signal. The frequency tracking loop tracks a frequency of the recovery clock signal to generate a frequency detection signal associated with the recovery clock signal. The phase lock loop receives the frequency detection signal and locks the recovery clock signal in a reference clock. The fast-locking unit generates a fast-locking signal according to the recovery clock signal and a first phase detection signal to allow the clock data recovery loop to quickly lock the data signal after the transition from a stall mode to the burst mode.
摘要翻译：突发模式时钟数据恢复装置包括时钟数据恢复环路，频率跟踪环路，频率跟踪环路和快速锁定单元。时钟数据恢复环路接收采样时钟信号和数据信号，并使用采样时钟信号锁定数据信号以产生恢复时钟信号。频率跟踪环路跟踪恢复时钟信号的频率，以产生与恢复时钟信号相关联的频率检测信号。锁相环接收频率检测信号，并将恢复时钟信号锁定在参考时钟中。快速锁定单元根据恢复时钟信号和第一相位检测信号产生快速锁定信号，以允许时钟数据恢复环路在从失速模式转换到突发模式之后快速锁定数据信号。

9. 发明申请

US20160344398A1 METHODS AND SYSTEMS FOR CASCADED PHASE-LOCKED LOOPS (PLLS) 审中-公开
标题翻译：嵌入式相位锁（PLLS）的方法和系统
公开(公告)号：US20160344398A1
公开(公告)日：2016-11-24
申请号：US15160496
申请日：2016-05-20
申请人： MaxLinear, Inc.
发明人： Prasun Kali Bhattacharyya , Prasenjit Bhowmik , Vamsi Paidi
IPC分类号： H03L7/23 , H03L7/089
CPC分类号： H03L7/235
摘要： Systems and methods are provided for cascaded phase-locked loops (PLLs). A plurality of phase-locked loops (PLLs) arranged in a cascaded manner may be used in providing enhanced signal generation. Each PLL generates an output based on a corresponding input and a feedback signal. The input to a first one of plurality of cascaded phase-locked loops (PLLs) comprises an input reference signal; the input to each remaining one of the plurality of the cascaded phase-locked loops (PLLs) corresponds to an output of a preceding one of the plurality of the cascaded phase-locked loops (PLLs); and the output of a last one of the plurality of cascaded phase-locked loops (PLLs) corresponds to an overall output signal of the plurality of cascaded phase-locked loops (PLLs). The frequency of the overall output signal is set based on the one or more adjustments applied in each one of the plurality of cascaded phase-locked loops (PLLs).
摘要翻译：为级联锁相环（PLL）提供系统和方法。以级联方式布置的多个锁相环（PLL）可用于提供增强的信号产生。每个PLL根据相应的输入和反馈信号产生输出。多个级联锁相环（PLL）中的第一个的输入包括输入参考信号; 对多个级联锁相环（PLL）中的每个剩余的一个的输入对应于多个级联锁相环（PLL）中的前一个的输出; 并且多个级联锁相环（PLL）中的最后一个的输出对应于多个级联锁相环（PLL）的总输出信号。基于在多个级联锁相环（PLL）中的每一个中施加的一个或多个调整来设置总输出信号的频率。

10. 发明申请

US20160269035A1 DUAL-LOOP PROGRAMMABLE AND DIVIDERLESS CLOCK GENERATOR FOR ULTRA LOW POWER APPLICATIONS 有权
标题翻译：用于超低功耗应用的双环可编程和无间断时钟发生器
公开(公告)号：US20160269035A1
公开(公告)日：2016-09-15
申请号：US15031115
申请日：2014-10-22
申请人： THE REGENTS OF THE UNIVERSITY OF MICHIGAN
发明人： David D. WENTZLOFF , Muhammad FAISAL
IPC分类号： H03L7/087 , H03L7/23 , H03L7/113 , H03L7/099
CPC分类号： H03L7/087 , H03B5/32 , H03B5/364 , H03L7/0991 , H03L7/0995 , H03L7/113 , H03L7/235 , H03L2207/50
摘要： A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.
摘要翻译：提供了一种可编程时钟发生器，特别适用于低功率应用。可编程时钟发生器包括：振荡器电路，其产生其频率由控制信号设置的输出信号，用于控制输出频率的两个反馈回路和选择哪个反馈回路在给定时间运行的回路选择。在操作中，频率环操作以粗调整输出信号的频率; 而相位运行则精细调节输出信号的频率。时钟发生器优选地由在亚阈值区域中或其附近操作的晶体管实现。

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