专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10147479B2 Memory module and memory system 有权
公开(公告)号：US10147479B2
公开(公告)日：2018-12-04
申请号：US15996974
申请日：2018-06-04
申请人： Longitude Semiconductor S.a.r.l.
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/06 , G11C11/408 , G11C5/04 , H01L23/538 , G11C8/12 , G11C5/00 , H01L25/18 , H01L25/065 , G11C29/48 , G11C29/26 , G11C29/12 , G11C7/10
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

2. 发明授权

US10037971B2 Semiconductor device having plural memory chip 有权
公开(公告)号：US10037971B2
公开(公告)日：2018-07-31
申请号：US15010930
申请日：2016-01-29
申请人： PS4 Luxco S.a.r.l.
发明人： Akira Ide
IPC分类号： G06F17/50 , H01L25/065 , H01L23/48 , G11C5/04 , H01L23/50 , G11C11/408
CPC分类号： H01L25/0657 , G11C5/04 , G11C11/408 , H01L23/481 , H01L23/50 , H01L2224/16145 , H01L2225/06544
摘要： A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions.

3. 再颁专利

USRE46798E1 Semiconductor device and manufacturing method therefor 有权
公开(公告)号：USRE46798E1
公开(公告)日：2018-04-17
申请号：US14267201
申请日：2014-05-01
申请人： PS4 LUXCO S.A.R.L.
发明人： Toshiyuki Hirota
IPC分类号： H01L27/108 , H01L21/20 , H01L49/02 , H01L27/02
CPC分类号： H01L28/60 , H01L27/0207 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

4. 发明授权

US09786762B2 Gate electrode of a semiconductor device, and method for producing same 有权
公开(公告)号：US09786762B2
公开(公告)日：2017-10-10
申请号：US14424943
申请日：2013-08-22
申请人： PS4 Luxco S.a.r.l.
发明人： Hiromu Yamaguchi , Kazuaki Tonari
IPC分类号： H01L29/78 , H01L29/51 , H01L29/49 , H01L21/8238 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L21/285
CPC分类号： H01L29/517 , H01L21/02164 , H01L21/02172 , H01L21/02667 , H01L21/28079 , H01L21/28088 , H01L21/28525 , H01L21/28568 , H01L21/82345 , H01L21/823828 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/513
摘要： A semiconductor device includes a semiconductor substrate; a gate insulating film provided on the semiconductor substrate; a gate electrode having a metal layer, a metal oxide layer and a silicon layer containing a dopant, provided sequentially on the gate insulating film; and a transistor having a gate insulating film and a gate electrode.

5. 发明授权

US09641175B2 Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit 有权
公开(公告)号：US09641175B2
公开(公告)日：2017-05-02
申请号：US15177646
申请日：2016-06-09
申请人： PS4 Luxco S.a.r.l.
发明人： Hiroki Fujisawa
IPC分类号： H03K19/00 , G01R31/317 , G11C11/4093 , G11C29/02 , G11C29/50
CPC分类号： H03H11/28 , G01R31/31713 , G11C11/4093 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , H03K19/0005
摘要： To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

6. 发明授权

US09576641B2 Semiconductor device verifying signal supplied from outside 有权
标题翻译：从外部提供的半导体器件验证信号
公开(公告)号：US09576641B2
公开(公告)日：2017-02-21
申请号：US14836315
申请日：2015-08-26
申请人： PS4 Luxco S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C11/408 , G11C7/24 , G11C11/4076 , G11C11/4078 , G11C11/4063 , G11C11/409 , G11C8/12
CPC分类号： G11C11/409 , G11C7/24 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4078 , G11C11/408 , G11C29/52
摘要： Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command.
摘要翻译：这里公开了一种半导体器件，其包括基于验证结果信号和外部命令产生内部命令的访问控制电路。外部命令指示访问控制电路访问第一电路的第一命令和允许访问控制电路不访问第一电路的第二命令中的至少一个，或者允许访问控制电路保持当前状态第一个电路。访问控制电路当验证结果信号指示第一逻辑电平时，基于外部命令生成内部命令。当验证结果信号指示第二逻辑电平时，访问控制电路即使外部命令指示第一命令也生成与第二命令相对应的内部命令。

7. 发明授权

US09571102B2 Semiconductor device having impedance calibration function to data output buffer and semiconductor module having the same 有权
标题翻译：具有对数据输出缓冲器和具有该阻抗校准功能的半导体模块的半导体器件
公开(公告)号：US09571102B2
公开(公告)日：2017-02-14
申请号：US14938351
申请日：2015-11-11
申请人： PS4 Luxco S.a.r.l.
发明人： Kentaro Hara
IPC分类号： H03K17/16 , H03K19/0185 , H03K19/003 , H03K19/0175 , G11C29/02 , G11C29/12 , G11C29/48 , G11C11/4093 , H03K19/00 , H03K19/094 , G11C11/40 , G11C11/4076
CPC分类号： H03K19/018557 , G11C11/40 , G11C11/4076 , G11C11/4093 , G11C11/4094 , G11C29/022 , G11C29/028 , G11C29/1201 , G11C29/48 , G11C2207/2254 , H01L2924/0002 , H03K19/0005 , H03K19/00315 , H03K19/017545 , H03K19/094 , H01L2924/00
摘要： Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.
摘要翻译：本文公开了一种半导体器件，其包括耦合到数据端子的第一晶体管单元和耦合到校准端子的多个第二晶体管单元。第一晶体管单元包括具有彼此并联连接的第一导电类型的多个第一晶体管，使得第一晶体管单元的阻抗是可调节的。每个第二晶体管单元包括具有彼此并联连接的第一导电类型的多个第二晶体管，使得每个第二晶体管单元的阻抗是可调节的。半导体器件还包括阻抗控制电路，其将每个第二晶体管单元的阻抗反映到第一晶体管单元。

8. 发明授权

US09570378B2 Semiconductor device including dummy pattern 有权
标题翻译：半导体器件包括虚拟图案
公开(公告)号：US09570378B2
公开(公告)日：2017-02-14
申请号：US14283050
申请日：2014-05-20
申请人： PS4 LUXCO S.A.R.L.
发明人： Yorio Takada
IPC分类号： G06F17/50 , H01L23/49 , H01L21/321 , H01L21/768 , H01L23/522 , H01L27/02 , H01L23/00
CPC分类号： H01L23/49 , H01L21/3212 , H01L21/7684 , H01L23/522 , H01L24/42 , H01L27/0207 , H01L2224/05599 , H01L2224/85399 , H01L2924/00014 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor device includes a substrate including a circuit region, a dummy region, and a dummy clearance section surrounding the circuit region, and a plurality of dummy patterns formed in the dummy region, the plurality of dummy patterns comprising a first dummy pattern and a second dummy pattern, a distance between the first dummy pattern and the circuit region being less than a distance between the second dummy pattern and the circuit region, and a dummy pattern being absent between the first dummy pattern and the circuit region. The first dummy pattern includes an area which is greater than an area of the second dummy pattern.
摘要翻译：一种半导体器件包括：基板，包括电路区域，虚拟区域和围绕电路区域的虚设间隙部分;以及形成在虚拟区域中的多个虚设图案，所述多个虚设图案包括第一虚设图案和第二虚拟图案虚拟图案，第一虚设图案和电路区域之间的距离小于第二虚设图案和电路区域之间的距离，并且在第一虚设图案和电路区域之间不存在虚设图案。第一虚拟图案包括大于第二虚设图案的区域的区域。

9. 发明授权

US09990982B2 Memory module and memory system 有权
公开(公告)号：US09990982B2
公开(公告)日：2018-06-05
申请号：US14476023
申请日：2014-09-03
申请人： Longitude Semiconductor S.a.r.l.
发明人： Yoshinori Matsui , Toshio Sugano , Hiroaki Ikeda
IPC分类号： G11C5/06 , G11C11/408 , G11C5/00 , G11C5/04 , G11C7/10 , G11C29/12 , G11C29/26 , G11C29/48 , H01L25/065 , H01L25/18 , G11C8/12 , H01L23/538
CPC分类号： G11C11/408 , G11C5/00 , G11C5/04 , G11C5/06 , G11C7/1051 , G11C7/1063 , G11C8/12 , G11C29/1201 , G11C29/26 , G11C29/48 , H01L23/5384 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00014 , H01L2224/0401
摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

10. 发明授权

US09715921B2 Semiconductor device having PDA function 有权
公开(公告)号：US09715921B2
公开(公告)日：2017-07-25
申请号：US15271872
申请日：2016-09-21
申请人： Longitude Semiconductor S.a.r.l.
发明人： Chikara Kondo
IPC分类号： G11C8/00 , G11C11/4093 , G11C7/10 , G11C7/22 , G11C11/4072 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C11/4063
CPC分类号： G11C11/4093 , G06F13/161 , G11C7/1045 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C11/4063 , G11C11/4072 , G11C11/4076 , G11C11/4087 , G11C11/4096 , Y02D10/14
摘要： A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式