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1. 发明授权

US11600323B2 Non-volatile memory device with concurrent bank operations 有权
公开(公告)号：US11600323B2
公开(公告)日：2023-03-07
申请号：US17246190
申请日：2021-04-30
申请人： Mosaid Technologies Incorporated
发明人： HakJune Oh , Hong Beom Pyeon , Jin-Ki Kim
IPC分类号： G11C11/56 , G11C7/10 , G11C16/10 , G11C16/26 , G06F1/12 , G11C16/16 , G11C16/34 , G11C16/06
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

2. 发明授权

US11594281B2 Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage 有权
公开(公告)号：US11594281B2
公开(公告)日：2023-02-28
申请号：US17154241
申请日：2021-01-21
申请人： Mosaid Technologies Incorporated
发明人： Chung-Zen Chen , Yang-Chieh Lin , Chung-Shan Kuo
IPC分类号： G11C16/14 , G11C16/16 , G11C16/08 , G11C16/02 , G11C16/04
摘要： A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal.

3. 发明申请

US20230046725A1 CLOCK MODE DETERMINATION IN A MEMORY SYSTEM 有权
公开(公告)号：US20230046725A1
公开(公告)日：2023-02-16
申请号：US17731408
申请日：2022-04-28
申请人： Mosaid Technologies Incorporated
发明人： Peter B. Gillingham , Graham Allan
IPC分类号： G06F3/06 , G06F13/16 , G11C7/10 , G11C7/22 , G11C16/10 , G11C16/28 , G11C16/32 , G11C16/04 , G11C14/00
摘要： A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

4. 发明申请

US20150092494A1 Vertical Gate Stacked NAND and Row Decoder for Erase Operation 有权
标题翻译：垂直门堆叠NAND和行解码器，用于擦除操作
公开(公告)号：US20150092494A1
公开(公告)日：2015-04-02
申请号：US14044449
申请日：2013-10-02
申请人： Mosaid Technologies Incorporated
发明人： Hyoung Seub Rhie
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14
摘要： A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.
摘要翻译：三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压以及对阵列中的位线结构的高通电压。

5. 发明申请

US20140133238A1 METHOD AND SYSTEM FOR PROGRAMMING NON-VOLATILE MEMORY WITH JUNCTIONLESS CELLS 有权
标题翻译：使用无连接电池编程非易失性存储器的方法和系统
公开(公告)号：US20140133238A1
公开(公告)日：2014-05-15
申请号：US13832785
申请日：2013-03-15
申请人： MOSAID TECHNOLOGIES INCORPORATED
发明人： Hyoung Seub Rhie
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483
摘要： A non-volatile memory system that has junctionless transistors is provided that uses suppression of the formation of an inversion-layer source and drain in the junctionless transistors to cause a discontinuous channel in at least one string. The system may include NAND flash memory cells composed of junctionless transistors, and has a set of wordlines. During program operation, a selected wordline of the set of wordlines is biased at a program voltage, and wordline voltage low enough to suppress the formation of source/drains is applied on at least one word line on a source side of the selected wordline such that a channel isolation occurs thereby causing the discontinuous channel in the at least string.
摘要翻译：提供了具有无连接晶体管的非易失性存储器系统，其使用抑制在无连接晶体管中形成反型层源极和漏极以在至少一个串中引起不连续通道。该系统可以包括由无连接晶体管组成的NAND闪存单元，并且具有一组字线。在编程操作期间，字母集合中的选定字线被偏置在编程电压上，并且低于足以抑制源极/漏极形成的字线电压被施加在所选字线的源极侧的至少一条字线上，使得发生通道隔离，从而导致至少串中的不连续通道。

6. 发明授权

US08713344B2 Methods and apparatus for clock signal synchronization in a configuration of series connected semiconductor devices 有权
标题翻译：在串联连接的半导体器件的配置中时钟信号同步的方法和装置
公开(公告)号：US08713344B2
公开(公告)日：2014-04-29
申请号：US12948186
申请日：2010-11-17
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G06F1/12
CPC分类号： G11C19/00 , G06F1/10 , H03L7/0812
摘要： A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device, and an output for providing a synchronized clock signal destined for a succeeding device. The device further includes a clock synchronizer for producing the synchronized clock signal by processing the received clock signal and an earlier version of the synchronized clock signal. The device further includes a device controller for adjusting a parameter used by the clock synchronizer in processing the earlier version of the synchronized clock signal. The system controller has an output for providing a first clock signal to a first device, and an input for receiving a second clock signal from a second device. The second clock signal corresponds to a version of the first clock signal that has undergone processing by a clock synchronizer in at least one of the devices. The system controller further includes a detector for processing the first and second clock signals to detect a phase difference therebetween; and a synchronization controller for commanding an adjustment to the clock synchronizer in at least one of the devices based on the phase difference detected by the detector.
摘要翻译：系统包括系统控制器和串联连接的半导体器件的配置。这种装置包括用于接收源自先前装置的时钟信号的输入端和用于提供去往后续装置的同步时钟信号的输出端。该装置还包括时钟同步器，用于通过处理所接收的时钟信号和较早版本的同步时钟信号来产生同步时钟信号。所述设备还包括设备控制器，用于在处理所述同步时钟信号的早期版本时调整由所述时钟同步器使用的参数。系统控制器具有用于向第一设备提供第一时钟信号的输出端和用于从第二设备接收第二时钟信号的输入端。第二时钟信号对应于在至少一个设备中由时钟同步器进行处理的第一时钟信号的版本。系统控制器还包括检测器，用于处理第一和第二时钟信号以检测它们之间的相位差; 以及同步控制器，用于基于由检测器检测到的相位差来指令至少一个设备中的时钟同步器的调整。

7. 发明授权

US08704569B2 Delay locked loop circuit and method 有权
标题翻译：延时锁相环电路及方法
公开(公告)号：US08704569B2
公开(公告)日：2014-04-22
申请号：US13718783
申请日：2012-12-18
申请人： MOSAID Technologies Incorporated
发明人： Dieter Haerle , Tony Mai , Peter Vlasenko
IPC分类号： H03L7/06
CPC分类号： H03L7/08 , H03L7/0812 , H03L7/0891 , H03L7/0895 , H03L7/095 , H03L7/10
摘要： A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.
摘要翻译：延迟锁定环包括初始化电路，其确保将DLL初始化为不接近延迟与控制电压特性的任一端的工作点。初始化电路强制DLL最初从初始延迟开始搜索锁定点，延迟在一个方向上变化，迫使DLL跳过第一个锁定点。初始化电路仅允许DLL改变从初始延迟到达到工作点的一个方向的电压控制延迟环的延迟。

8. 发明申请

US20140105113A1 Network Architecture for Data Communication 有权
标题翻译：数据通信网络架构
公开(公告)号：US20140105113A1
公开(公告)日：2014-04-17
申请号：US14135167
申请日：2013-12-19
申请人： MOSAID Technologies Incorporated
发明人： Antonio Francescon , Davide Mandato
IPC分类号： H04W24/02 , H04W88/06
CPC分类号： G05F1/66 , H04W24/00 , H04W24/02 , H04W24/04 , H04W88/06 , H04W88/08
摘要： This invention relates to a network architecture for data communication between data sources and data destinations via network nodes and at least one data concentrator. According to the invention the nodes (2, 4) are conceived to communicate with a data concentrator (1) in both directions either via a permanently operative network (8) in the multihop mode or via an occasionally operative network (5) in wireless connection with mobile user nodes (6) in the nomadic mode. Means for commutation are provided to detect faulty multihop nodes and to activate nomadic nodes instead until the fault disappears, in order to maintain the overall functionality of the network. Moreover the network according to the invention allows to share the data collected by mobile users with other mobile users, thus forming a peer-to-peer network.
摘要翻译：本发明涉及用于经由网络节点和至少一个数据集中器的数据源和数据目的地之间的数据通信的网络架构。根据本发明，节点（2,4）被设想为在多重模式下经由永久操作的网络（8）或经由无线连接中的偶尔操作的网络（5）在两个方向上与数据集中器（1）进行通信移动用户节点（6）处于游牧模式。提供换向的手段来检测故障多跳节点并激活游牧节点，直到故障消失为止，以维持网络的整体功能。此外，根据本发明的网络允许与其他移动用户共享移动用户收集的数据，从而形成对等网络。

9. 发明授权

US08694692B2 Apparatus and method for producing device identifiers for serially interconnected devices of mixed type 有权
标题翻译：用于生产混合型串联互连设备的设备标识符的设备和方法
公开(公告)号：US08694692B2
公开(公告)日：2014-04-08
申请号：US13671248
申请日：2012-11-07
申请人： Mosaid Technologies Incorporated
发明人： Hong Beom Pyeon , HakJune Oh , Jin-Ki Kim , Shuji Sumi
IPC分类号： G06F3/00
CPC分类号： G06F13/4243
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no-match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND-，NOR-和AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不为另一设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。

10. 发明申请

US20140093057A1 OUTLET ADD-ON MODULE 审中-公开
标题翻译： OUTLET ADD-ON模块
公开(公告)号：US20140093057A1
公开(公告)日：2014-04-03
申请号：US14057724
申请日：2013-10-18
申请人： MOSAID Technologies Incorporated
发明人： Ami HAZANI , Shlomo BUTBUL , Rafael Gil KOBY , Yehuda BINDER
IPC分类号： H04B3/54
CPC分类号： H04B3/542 , H01R13/719 , H01R31/065 , H04B2203/5408
摘要： A method and an apparatus for upgrading an existing service outlet (e.g. LAN, telephone, power or CATV outlet) in a house by adding functionality thereto. The functionality is added by an add-on module, connected electrically and secured mechanically to the existing outlet. Several attachment devices are exampled, including surface attachment, side clamping, snap locking, strap securing and fastening screws. The add-on module may include a service connector for retaining the basic existing outlet function. The module may be attached in a permanent way or by using a detachable solution.
摘要翻译：一种用于通过向其添加功能来升级房屋中的现有服务插座（例如LAN，电话，电源或CATV插座）的方法和装置。该功能由附加模块添加，电连接并机械地连接到现有插座。示例中包括几个附件，包括表面附件，侧面夹紧，卡扣锁定，皮带固定和紧固螺丝。附加模块可以包括用于保持基本现有插座功能的服务连接器。模块可以以永久的方式连接或通过使用可拆卸的解决方案。

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