专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20140340133A1 RADIATION HARDENED CIRCUIT 审中-公开
标题翻译：辐射硬化电路
公开(公告)号：US20140340133A1
公开(公告)日：2014-11-20
申请号：US14276567
申请日：2014-05-13
申请人： STMicroelectronics (Crolles 2) SAS , STMicroelectronics Pvt. Ltd.
发明人： Gilles Gasiot , Sylvain Clerc , Junaid Yousuf , Maximilien Glorieux
IPC分类号： H03K19/003 , H03L7/08
CPC分类号： H03K19/0033 , G11C5/005 , H03K3/0375 , H03K3/356121 , H03L7/08 , H03L7/0891 , H03L7/0896 , H03L7/095 , H03L7/18
摘要： A circuit including a data storage element; first and second input circuitry coupled respectively to first and second inputs of the data storage element and each including a plurality of components adapted to generate, as a function of an initial signal, first and second input signals respectively provided to the first and second inputs; wherein the data storage element includes a first storage node and is configured such that a voltage state stored at the first storage node is protected from a change in only one of the first and second input signals by being determined by the conduction state of a first transistor coupled to the first storage node and controlled based on the first input signal and by the conduction state of a second transistor coupled to the first storage node and controlled based on the second input signal.
摘要翻译：一种包括数据存储元件的电路; 第一和第二输入电路分别耦合到数据存储元件的第一和第二输入端，并且每个输入电路包括适于产生分别提供给第一和第二输入的第一和第二输入信号作为初始信号的函数的多个分量; 其中所述数据存储元件包括第一存储节点，并且被配置为使得通过由第一晶体管的导通状态来确定存储在所述第一存储节点处的电压状态以防止所述第一和第二输入信号中仅一个的变化耦合到所述第一存储节点并且基于所述第一输入信号以及耦合到所述第一存储节点的第二晶体管的导通状态并基于所述第二输入信号进行控制。

2. 发明授权

US08805081B2 Object detection in an image 有权
标题翻译：图像中的对象检测
公开(公告)号：US08805081B2
公开(公告)日：2014-08-12
申请号：US13100081
申请日：2011-05-03
申请人： Ludovic Chotard , Michel Sanches , Vitor Schwambach , Mahesh Chandra
发明人： Ludovic Chotard , Michel Sanches , Vitor Schwambach , Mahesh Chandra
IPC分类号： G06K9/46
CPC分类号： G06K9/00228 , G06K9/6257
摘要： The invention concerns a method of performing, by an image processing device, object detection in an image comprising: performing one or more tests of a test sequence for detection of a first object on pixels values of a plurality of at least partially overlapping sub-regions (310, 312, 314) of a first search window (108); generating a cumulative score based on results of said one or more tests on said plurality of sub-regions; comparing said cumulative score with a threshold value; and based on said comparison, selectively performing one or more of said tests of said test sequence on at least one further sub-region of said first search window, said at least one further sub-region at least partially overlapping each of said plurality of sub-regions.
摘要翻译：本发明涉及一种通过图像处理设备执行图像中的对象检测的方法，包括：对多个至少部分重叠的子区域的像素值执行用于检测第一对象的测试序列的一个或多个测试（108,312）的第一搜索窗口（310,312,314）; 基于对所述多个子区域的所述一个或多个测试的结果生成累积分数; 将所述累积分数与阈值进行比较; 并且基于所述比较，在所述第一搜索窗口的至少一个另外的子区域上选择性地执行所述测试序列的所述测试中的一个或多个，所述至少一个另外的子区域至少部分地与所述多个子区域区域。

3. 发明授权

US08793228B2 File system including a file header area and a file data area 有权
标题翻译：文件系统包括文件头部区域和文件数据区域
公开(公告)号：US08793228B2
公开(公告)日：2014-07-29
申请号：US12353563
申请日：2009-01-14
申请人： Vipin Bansal , Deepak Naik , Raunaque Quaiser , Alok Kumar Mittal
发明人： Vipin Bansal , Deepak Naik , Raunaque Quaiser , Alok Kumar Mittal
IPC分类号： G06F7/00 , G06F17/30 , G06F12/00 , G06F17/00
CPC分类号： G06F17/30218
摘要： A system includes a storage subsystem having a data area and a header area. The data area is for storing contents of at least one data file, and the header area is for storing access parameters and status information for accessing each data file individually. The data area and the header area define a storage area in the storage subsystem. Multiple files are efficiently managed based on utilization of the storage area in the storage subsystem.
摘要翻译：系统包括具有数据区和报头区的存储子系统。数据区用于存储至少一个数据文件的内容，并且标题区用于存储用于单独访问每个数据文件的访问参数和状态信息。数据区和标题区定义存储子系统中的存储区。基于存储子系统中存储区域的利用率，有效地管理多个文件。

4. 发明申请

US20130308399A1 WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY 有权
标题翻译：自适应存储器的自写时序电路
公开(公告)号：US20130308399A1
公开(公告)日：2013-11-21
申请号：US13474825
申请日：2012-05-18
申请人： Nishu Kohli
发明人： Nishu Kohli
IPC分类号： G11C7/22
CPC分类号： G11C11/5621 , G11C7/227 , G11C11/413 , G11C11/419 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/0475
摘要： A self-timed memory includes a plurality of write timer cells. A reference write driver circuit writes a logic low value to a true side of the write timer cells. Each write timer cell includes a pullup transistor whose gate is coupled to an internal true node. Self-timing is effectuated by detecting a completion of the logic value write at a complement side of the write timer cells and signaling a reset of the self-timer memory in response to detected completion. To better align detected completion of the write in write timer cells to actual completion of a write in the memory, a gate to source voltage of the write timer cell pullup transistor is lowered by increasing a lower logic level voltage at the internal true node in connection with driver circuit operation to write a low logic state into the true side of the write timer cell.
摘要翻译：自定时存储器包括多个写入定时器单元。参考写入驱动器电路将逻辑低电平写入写入定时器单元的真实侧。每个写入定时器单元包括其栅极耦合到内部真实节点的上拉晶体管。通过检测在写定时器单元的补码侧的逻辑值写入的完成并响应于检测到的完成而发信号通知自拍定时器存储器的复位来实现自定时。为了更好地调整写入定时器单元中的写入完成与存储器中写入的实际完成，通过在连接的内部真实节点处增加较低的逻辑电平电平来降低写入定时器单元上拉晶体管的栅极到源极电压通过驱动电路操作将低逻辑状态写入写定时器单元的真实面。

5. 发明申请

US20130181754A1 HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY 有权
标题翻译：高抖动和频率干扰容忍时钟数据恢复
公开(公告)号：US20130181754A1
公开(公告)日：2013-07-18
申请号：US13784571
申请日：2013-03-04
申请人： STMicroelectronics Pvt. Ltd.
发明人： Nitin GUPTA
IPC分类号： H03L7/199
CPC分类号： H03L7/199 , H03L7/0807 , H03L7/0812 , H03L7/091 , H04L7/0337
摘要： In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period.
摘要翻译：在从接收到的数字数据流中恢复基座的方法以及从接收的数字数据流中恢复时钟的装置中，从接收器的基座产生相移的停靠信号。在选择一个相移时钟信号之后，确定另外两个相移时钟信号。根据在三个选定的相移时钟信号的上升沿/下降沿采集的采样值，增加和比较计数器值。如果需要，相移时钟信号的选择和对输入数字数据流进行采样的步骤，比较值和增加计数器值，直到计数器值的比较结果指示后一个确定的相位时钟信号之一，移位的时钟信号在接收到的位数周期的中心选通接收到的数字数据流。

6. 发明申请

US20130170081A1 TRIGGER CIRCUIT AND METHOD OF USING SAME 有权
标题翻译：触发电路及其使用方法
公开(公告)号：US20130170081A1
公开(公告)日：2013-07-04
申请号：US13626131
申请日：2012-09-25
申请人： STMICROELECTRONICS PVT LTD
发明人： Gaurav Singh
IPC分类号： H02H9/00
CPC分类号： H02H9/046
摘要： A circuit includes a discharge arrangement configured to discharge an electrostatic charge. The discharge arrangement has a discharge state. A first circuit is configured to provide a pulse to the discharge arrangement when the electrostatic charge is sensed. The pulse causes the discharge arrangement to enter the discharge state. A second circuit is configured to maintain the discharge arrangement in the discharge state after the pulse has ended. A third circuit is configured to receive the pulse and to provide a delayed output to the discharge arrangement. The delayed output causes the discharge arrangement to exit the discharge state.
摘要翻译：电路包括被配置为放电静电电荷的放电装置。放电装置具有放电状态。第一电路被配置为当感测静电电荷时向放电装置提供脉冲。脉冲使排出装置进入排出状态。第二电路被配置为在脉冲结束之后将放电配置保持在放电状态。第三电路被配置为接收脉冲并向放电装置提供延迟的输出。延迟输出导致放电装置退出放电状态。

7. 发明申请

US20130135914A1 XY TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) CELL AND ARRAY 有权
标题翻译： XY内容可寻址存储器（TCAM）单元和阵列
公开(公告)号：US20130135914A1
公开(公告)日：2013-05-30
申请号：US13307167
申请日：2011-11-30
申请人： Nishu Kohli
发明人： Nishu Kohli
IPC分类号： G11C15/04
CPC分类号： G11C15/04 , G11C5/02 , G11C5/025 , G11C5/06 , G11C5/063 , G11C11/412 , G11C15/00 , H01L27/00 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A ternary content addressable memory (TCAM) is formed by TCAM cells that are arranged in an array. Each TCAM cell includes a first and second SRAM cells and a comparator. The SRAM cells predominantly in use have a horizontal topology with a rectangular perimeter defined by longer and shorter side edges. The match lines for the TCAM extend across the array, and are coupled to TCAM cells along an array column. The bit lines extend across the array, and coupled to TCAM cells along an array row. Each match line is oriented in a first direction (the column direction) that is parallel to the shorter side edge of the horizontal topology layout for the SRAM cells in each CAM cell. Each bit line is oriented in a second direction (the row direction) that is parallel to the longer side edge of the horizontal topology layout for the SRAM cells in each CAM cell.
摘要翻译：三元内容可寻址存储器（TCAM）由排列成阵列的TCAM单元形成。每个TCAM单元包括第一和第二SRAM单元和比较器。主要使用的SRAM单元具有由较长和较短侧边限定的矩形周长的水平拓扑。 TCAM的匹配行扩展到阵列，并且沿阵列列耦合到TCAM单元。位线延伸穿过阵列，并且沿阵列行耦合到TCAM单元。每个匹配线在与每个CAM单元中的SRAM单元的水平拓扑布局的平行于较短边缘的第一方向（列方向）上取向。每个位线在与每个CAM单元中的SRAM单元的水平拓扑布局的较长边缘平行的第二方向（行方向）上取向。

8. 发明申请

US20130124121A1 BATTERY PACK MANAGEMENT 有权
标题翻译：电池组管理
公开(公告)号：US20130124121A1
公开(公告)日：2013-05-16
申请号：US13294299
申请日：2011-11-11
申请人： K. R. Hariharasudhan , Frank J. Sigmund
发明人： K. R. Hariharasudhan , Frank J. Sigmund
IPC分类号： G01R31/36 , G06F19/00 , G01N27/416
CPC分类号： G01R31/3651 , G01R31/3624
摘要： A battery pack management system provides information such as remaining capacity and/or run time to empty for a battery. A time taken for a battery voltage to drop a threshold amount is measured and used to determine a remaining capacity of the battery. The time may be associated with a temperature and current of the battery. The remaining capacity of a battery is calculated by monitoring a discharge of the battery. For example, current drawn from the battery is monitored over a period of time and an initial amount by which the battery has been discharged is calculated. Compensation of this initial amount is carried out in order to take into account factors such as temperature, self-discharge rate and age of the battery.
摘要翻译：电池组管理系统提供诸如电池剩余容量和/或运行时间的信息。测量电池电压下降阈值所用的时间并用于确定电池的剩余容量。该时间可能与电池的温度和电流相关。通过监视电池的放电来计算电池的剩余容量。例如，在一段时间内监视从电池吸取的电流，并计算电池已经放电的初始量。为了考虑到电池的温度，自放电率和使用寿命等因素，进行该初始量的补偿。

9. 发明授权

US08421519B2 Switched charge storage element network 有权
标题翻译：开关电荷存储元件网络
公开(公告)号：US08421519B2
公开(公告)日：2013-04-16
申请号：US12615991
申请日：2009-11-10
申请人： Chandrajit Debnath , Anubhuti Rangbulla
发明人： Chandrajit Debnath , Anubhuti Rangbulla
IPC分类号： H03K5/00
CPC分类号： G06G7/18
摘要： A switched charge storage element integrator in a continuous or discrete time circuit, the integrator including a differential input amplifier, a first 2-terminal charge storage element, a second 2-terminal charge storage element, and a plurality of controlled switches. The differential input amplifier is coupled to a capacitor and a resistor and configured as an inverting integrator. An inverting terminal of the amplifier is coupled to two controlled switches. A non-inverting terminal of the amplifier is coupled to a reference voltage. The first and second switched charge storage element blocks are alternatingly coupled to the inverting terminal INM of the amplifier XOPA during the active state of a second clock signal and a first clock signal, respectively, for making the supply noise continuous and eliminating its dependency on the clock phases, thereby zeroing its convolution with the clock signal.
摘要翻译：一种在连续或离散时间电路中的开关电荷存储元件积分器，所述积分器包括差分输入放大器，第一2端电荷存储元件，第二二端电荷存储元件和多个受控开关。差分输入放大器耦合到电容器和电阻器，并被配置为反相积分器。放大器的反相端子耦合到两个受控开关。放大器的非反相端子耦合到参考电压。第一和第二开关电荷存储元件块分别在第二时钟信号和第一时钟信号的有效状态下交替耦合到放大器XOPA的反相端INM，以使供电噪声连续并且消除其对时钟相位，从而使其与时钟信号的卷积归零。

10. 发明申请

US20130083247A1 VIDEO DECODER 有权
标题翻译：视频解码器
公开(公告)号：US20130083247A1
公开(公告)日：2013-04-04
申请号：US13250581
申请日：2011-09-30
申请人： Ravindranath Ramalingaiah MUNNAN
发明人： Ravindranath Ramalingaiah MUNNAN
IPC分类号： H04N9/455
CPC分类号： H04N9/455
摘要： A video decoder that separates and analyzes analog video signals includes a hue and saturation separator and a video signal determiner. The hue and saturation separator demodulates from a component video signal chroma signal, which includes a hue signal and a saturation signal. The video signal determiner determines at least one video signal characteristic of the component video signal dependent on the hue and saturation signal. The video signal determiner may include a mode determiner that determines the encoding standard of the video signal, and a color burst determiner that determines a location of a color burst signal with the video signal. The mode determiner may include a signal lock detector, a sequence matcher, and an encoding mode selector. The color burst determiner may include an absolute value determiner and a burst position determiner.
摘要翻译：分离和分析模拟视频信号的视频解码器包括色相和饱和分离器以及视频信号确定器。色相和饱和度分离器从包括色相信号和饱和信号的分量视频信号色度信号解调。视频信号确定器根据色相和饱和度信号确定分量视频信号的至少一个视频信号特性。视频信号确定器可以包括确定视频信号的编码标准的模式确定器以及用视频信号确定色同步信号的位置的色同步确定器。模式确定器可以包括信号锁定检测器，序列匹配器和编码模式选择器。色同步确定器可以包括绝对值确定器和突发位置确定器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式