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1. 发明申请

US20170366193A1 PROGRAMMABLE FREQUENCY DIVIDER, PLL SYNTHESIZER AND RADAR DEVICE 审中-公开
公开(公告)号：US20170366193A1
公开(公告)日：2017-12-21
申请号：US15609925
申请日：2017-05-31
申请人： FUJITSU LIMITED
发明人： Hiroshi Matsumura
IPC分类号： H03L7/199 , H03K23/66 , G01S7/02
CPC分类号： H03L7/199 , G01S7/02 , G01S7/03 , G01S7/35 , H03K23/667 , H03L7/1974
摘要： A programmable frequency divider includes a modulus frequency divider, a pulse counter, and a swallow counter. The pulse counter is configured to count an output signal from the modulus frequency divider, and output a frequency division signal, and the swallow counter is configured to count the output signal from the modulus frequency divider and perform resetting on the basis of the frequency division signal from the pulse counter, the programmable frequency divider being configured to control the modulus frequency divider on the basis of a signal from the swallow counter. The programmable frequency divider includes a control signal delay circuit, disposed between an output terminal of the swallow counter and a control terminal of the modulus frequency divider, configured to delay a signal from the swallow counter, and generate a control signal for controlling the modulus frequency divider.

2. 发明授权

US09503109B2 Apparatus and methods for synchronizing phase-locked loops 有权
公开(公告)号：US09503109B2
公开(公告)日：2016-11-22
申请号：US14726913
申请日：2015-06-01
申请人： ANALOG DEVICES GLOBAL
发明人： David J. McLaurin , Christopher W. Angell , Michael F. Keaveney
IPC分类号： H03K3/013 , H03L7/081 , H03L7/197 , H03L7/085 , H03L7/10 , H03L7/199 , H03L7/23
CPC分类号： H03L7/1976 , H03L7/085 , H03L7/104 , H03L7/199 , H03L7/23
摘要： Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

3. 发明授权

US08749283B2 PLL dual edge lock detector 有权
标题翻译： PLL双边缘锁定检测器
公开(公告)号：US08749283B2
公开(公告)日：2014-06-10
申请号：US14100274
申请日：2013-12-09
申请人： Marvell World Trade Ltd.
发明人： Xiaoyue Wang , Shafiq M. Jamal
IPC分类号： H03L7/18 , H03L7/093
CPC分类号： H03L7/095 , H03L7/199
摘要： A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.
摘要翻译：指示目标信号与参考信号同相的锁定信号包括在目标信号的上升沿和下降沿检测参考信号。在参考信号的上升沿和下降沿检测目标信号。使用目标和参考信号之间的相位不同的状态将定时装置置于复位状态。当定时装置被允许超时时，确定信号被指示目标信号被认为被锁定到参考信号。

4. 发明申请

US20140097879A1 PLL DUAL EDGE LOCK DETECTOR 有权
标题翻译： PLL双边锁定检测器
公开(公告)号：US20140097879A1
公开(公告)日：2014-04-10
申请号：US14100274
申请日：2013-12-09
申请人： Marvell World Trade Ltd.
发明人： Xiaoyue Wang , Shafiq M. Jamal
IPC分类号： H03L7/095
CPC分类号： H03L7/095 , H03L7/199
摘要： A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.
摘要翻译：指示目标信号与参考信号同相的锁定信号包括在目标信号的上升沿和下降沿检测参考信号。在参考信号的上升沿和下降沿检测目标信号。使用目标和参考信号之间的相位不同的状态将定时装置置于复位状态。当定时装置被允许超时时，确定信号被指示目标信号被认为被锁定到参考信号。

5. 发明授权

US08681918B2 High jitter and frequency drift tolerant clock data recovery 有权
标题翻译：高抖动和频率漂移容限时钟数据恢复
公开(公告)号：US08681918B2
公开(公告)日：2014-03-25
申请号：US13784571
申请日：2013-03-04
申请人： STMicroelectronics International N.V.
发明人： Nitin Gupta
IPC分类号： H04L7/00
CPC分类号： H03L7/199 , H03L7/0807 , H03L7/0812 , H03L7/091 , H04L7/0337
摘要： In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the center of a bit period.
摘要翻译：在从接收到的数字数据流中恢复基座的方法以及从接收的数字数据流中恢复时钟的装置中，从接收器的基座产生相移的停靠信号。在选择一个相移时钟信号之后，确定另外两个相移时钟信号。根据在三个选定的相移时钟信号的上升沿/下降沿采集的采样值，增加和比较计数器值。如果需要，相移时钟信号的选择和对输入数字数据流进行采样的步骤，比较值和增加计数器值，直到计数器值的比较结果指示后一个确定的相位时钟信号之一，移位的时钟信号在接收到的位数周期的中心选通接收到的数字数据流。

6. 发明授权

US08138842B2 PLL frequency synthesizer 有权
标题翻译： PLL频率合成器
公开(公告)号：US08138842B2
公开(公告)日：2012-03-20
申请号：US12560118
申请日：2009-09-15
申请人： Masafumi Kondou , Toshihiko Mori
发明人： Masafumi Kondou , Toshihiko Mori
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/099 , H03L7/199
摘要： A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.
摘要翻译：频率合成器包括压控振荡器，频率范围调谐电路，其检测设置与可变设定的分频比相对应的压控振荡器的压控频率范围的频率控制码，以及频率控制代码存储器，其存储由与分频比对应的频率范围调谐电路检测的频率控制代码。在初始化间隔中，频率范围调谐电路检测与可分别设定的分频比对应的频率控制码，频率控制码存储器存储检测出的频率控制码。在正常操作间隔中，响应于频率选择信号，存储在频率控制代码存储器中并对应于可变设定的分频比的频率控制代码被输出到压控振荡器。

7. 发明授权

US07684532B2 Clock data recovery circuitry associated with programmable logic device circuitry 有权
标题翻译：与可编程逻辑器件电路相关的时钟数据恢复电路
公开(公告)号：US07684532B2
公开(公告)日：2010-03-23
申请号：US11796136
申请日：2007-04-25
申请人： Edward Aung , Henry Lui , Paul Butler , John Turner , Rakesh Patel , Chong Lee
发明人： Edward Aung , Henry Lui , Paul Butler , John Turner , Rakesh Patel , Chong Lee
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , G11C7/222 , H03K19/17732 , H03K19/17744 , H03L7/07 , H03L7/0802 , H03L7/0814 , H03L7/089 , H03L7/0891 , H03L7/0995 , H03L7/187 , H03L7/199 , H03M9/00 , H04L7/0025 , H04L7/02 , H04L7/0337
摘要： A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.
摘要翻译：可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行增强，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者它可以全部或部分地在单独的集成电路上。电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。电路可以是较大系统的一部分。

8. 发明申请

US20100007425A1 PLL FREQUENCY SYNTHESIZER 有权
标题翻译： PLL频率合成器
公开(公告)号：US20100007425A1
公开(公告)日：2010-01-14
申请号：US12560118
申请日：2009-09-15
申请人： Masafumi KONDOU , Toshihiko MORI
发明人： Masafumi KONDOU , Toshihiko MORI
IPC分类号： H03L7/18
CPC分类号： H03L7/10 , H03L7/099 , H03L7/199
摘要： A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.
摘要翻译：频率合成器包括压控振荡器，频率范围调谐电路，其检测设置与可变设定的分频比相对应的压控振荡器的压控频率范围的频率控制码，以及频率控制代码存储器，其存储由与分频比对应的频率范围调谐电路检测的频率控制代码。在初始化间隔中，频率范围调谐电路检测与可分别设定的分频比对应的频率控制码，频率控制码存储器存储检测出的频率控制码。在正常操作间隔中，响应于频率选择信号，存储在频率控制代码存储器中并对应于可变设定的分频比的频率控制代码被输出到压控振荡器。

9. 发明申请

US20080248771A1 CALIBRATION TECHNIQUES FOR FREQUENCY SYNTHESIZERS 有权
标题翻译：频率合成器的校准技术
公开(公告)号：US20080248771A1
公开(公告)日：2008-10-09
申请号：US12140523
申请日：2008-06-17
申请人： Jeremy D. Dunworth , Brett C. Walker
发明人： Jeremy D. Dunworth , Brett C. Walker
IPC分类号： H04B1/06
CPC分类号： H03L7/0898 , H03L7/099 , H03L7/113 , H03L7/199
摘要： In one embodiment, this disclosure describes a frequency synthesizer for use in a wireless communication device, or similar device that requires precision frequency synthesis but small amounts of noise. In particular, the frequency synthesizer may include a phase locked loop (PLL) and an integrated voltage controlled oscillator (VCO). The frequency synthesizer may implement one or more calibration techniques to quickly and precisely calibrate the VCO. In this manner, the analog gain of the VCO can be significantly reduced, which may improve performance of the wireless communication device. Also, the initial state of the PLL may be improved to reduce lock time of the PLL, which may enhance performance of the wireless communication device.
摘要翻译：在一个实施例中，本公开描述了一种在无线通信设备中使用的频率合成器或需要精确频率合成但是具有少量噪声的类似设备。特别地，频率合成器可以包括锁相环（PLL）和集成压控振荡器（VCO）。频率合成器可以实现一种或多种校准技术来快速且精确地校准VCO。以这种方式，可以显着地减小VCO的模拟增益，这可以提高无线通信设备的性能。此外，可以改善PLL的初始状态以减少PLL的锁定时间，这可以增强无线通信设备的性能。

10. 发明授权

US07423493B2 Wireless communication semiconductor integrated circuit device and mobile communication system 失效
公开(公告)号：US07423493B2
公开(公告)日：2008-09-09
申请号：US11501778
申请日：2006-08-10
申请人： Toshiya Uozumi , Hirotaka Osawa , Jiro Shinbo , Satoru Yamamoto
发明人： Toshiya Uozumi , Hirotaka Osawa , Jiro Shinbo , Satoru Yamamoto
IPC分类号： H03L7/18
CPC分类号： H03L7/099 , H03L7/0891 , H03L7/10 , H03L7/199
摘要： An RF IC in which a PLL circuit including a loop filter is incorporated into a semiconductor chip is achieved without increasing power consumption or chip size. The RF IC includes a VCO capable of switching oscillation frequency bands, a variable frequency divider, a phase comparator, and a loop filter, which are contained in the PLL loop. A discrimination circuit discriminates a lead or lag in a phase of an output signal from the variable frequency divider against a reference signal and an automatic band selecting circuit generates a signal for switching the frequency bands of the VCO based on output from the discrimination circuit. While switching the frequency bands of the VCO by means of bisection algorithm, the RF IC detects an optimum frequency band, and adds offset to it to determine a final usable frequency band.

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