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1. 发明授权

US11545998B2 Offset value determination in a check node processing unit for message-passing decoding of non-binary codes 有权
公开(公告)号：US11545998B2
公开(公告)日：2023-01-03
申请号：US17276255
申请日：2019-10-07
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Hassan Harb , Emmanuel Boutillon , Cédric Marchand
IPC分类号： H03M13/11 , H03M13/00
摘要： Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).

2. 发明申请

US20170317695A1 METHODS AND DEVICES FOR ERROR CORRECTING CODES DECODING 审中-公开
公开(公告)号：US20170317695A1
公开(公告)日：2017-11-02
申请号：US15498589
申请日：2017-04-27
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Cédric MARCHAND , Emmanuel BOUTILLON
IPC分类号： H03M13/37 , H03M13/15 , H03M13/11
CPC分类号： H03M13/3746 , H03M13/1102 , H03M13/1117 , H03M13/1171 , H03M13/1575 , H03M13/6502
摘要： Embodiments of the invention provide a check node processing unit implemented in a decoder, said decoder being configured to decode a signal encoded using an error correcting code, said signal comprising symbols, the check node processing unit being configured to receive at least two input messages and to generate at least one output message, each message comprising a plurality of components, each component comprising a value of a symbol and a reliability metrics associated with said symbol, wherein the check node processing unit comprises: a data structure (31) configured to store said input messages, the components of the input messages being associated with an integer index in the data structure; a data processing unit (33) configured to apply one or more iterations of a transformation operation to at least a part of the data structure, each iteration of the transformation operation being performed to arrange the components of said input messages in said data structure (31) depending on at least some of the components of the messages associated with a given value of the integer index, which provides a transformed data structure; a calculation unit (35) configured to determine said at least one output message from the components comprised in said transformed data structure.

3. 发明申请

US20160336967A1 DECODING OF NON-BINARY LDPC CODES 审中-公开
标题翻译：非二进制LDPC编码的解码
公开(公告)号：US20160336967A1
公开(公告)日：2016-11-17
申请号：US15110349
申请日：2015-01-07
申请人： UNIVERSITE DE BRETAGNE SUD , CENTER NATIONAL DE LA RECHERCHE SCIENTIFIQUE - CNRS -
发明人： Emmanuel Boutillon , Oussama Abassi , Laura Conde-Canencia
IPC分类号： H03M13/11
CPC分类号： H03M13/1128 , H03M13/1117 , H03M13/1171
摘要： A method is proposed for managing a parity-check node calculation unit of an error-correcting code decoder having a nrepresentation as a bipartite graph comprising at least one parity-check node, the parity-check node being configured to receive first and second input messages, and to produce an output message, the elements of the input and output messages of the parity-check N node comprising a symbol and a measure of reliability associated with the symbol, the first and second input messages containing lists of elements ordered by their measure of reliability. The method comprises: initializing a plurality of nbub FIFO memories with elements calculated from combinations of elements of the first and second input messages, and iteratively determining the values of the output message.
摘要翻译：提出一种用于管理纠错码解码器的奇偶校验节点计算单元的方法，所述纠错码解码器具有作为包括至少一个奇偶校验节点的二分图的n表示，所述奇偶校验节点被配置为接收第一和第二输入消息并且为了产生输出消息，奇偶校验N节点的输入和输出消息的元素包括与该符号相关联的符号和可靠性度量，第一和第二输入消息包含由其度量所排序的元素列表的可靠性。该方法包括：通过从第一和第二输入消息的元素的组合计算的元素来初始化多个nbub FIFO存储器，并迭代地确定输出消息的值。

4. 发明授权

US08645787B2 Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor 有权
标题翻译：用于控制非二进制LDPC码解码器的基本奇偶校验节点的方法，以及对应的基本奇偶校验节点处理器
公开(公告)号：US08645787B2
公开(公告)日：2014-02-04
申请号：US13319033
申请日：2010-05-05
申请人： Emmanuel Boutillon , Laura Conde-Canencia
发明人： Emmanuel Boutillon , Laura Conde-Canencia
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/1171 , H03M13/1117 , H03M13/6502 , H03M13/6505
摘要： A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1, U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm′ elements sorted in said ascending or descending order, nm′ being greater than 1, each element of the output list (Uout) being the result of a computing operation φ between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.
摘要翻译：一种用于控制解码器的基本奇偶校验节点的方法，用于使用至少一个非二进制奇偶校验约束来解码非二进制LDPC码或码解码器，以及相应的基本奇偶校验节点。基本奇偶校验节点接收具有按升序或降序排列的nm个元素的第一和第二输入列表（U1，U2），其中nm大于1，并且给出以所述升序或降序排列的nm'元素的输出列表（Uout），nm'大于1，输出列表（Uout）的每个元素是第一输入列表（U1）的元素和第二输入列表（U2）的元素之间的计算操作phi的结果。选择要生成的输出列表的每个元素的有限数量的候选，以便减少要在基本奇偶校验节点中执行的操作的数量。

5. 发明申请

US20090067445A1 ROUTER AND ROUTING NETWORK 审中-公开
标题翻译：路由器和路由网络
公开(公告)号：US20090067445A1
公开(公告)日：2009-03-12
申请号：US12091830
申请日：2006-10-27
申请人： Jean-Philippe Diguet , Samuel Evain
发明人： Jean-Philippe Diguet , Samuel Evain
IPC分类号： H04L12/56
CPC分类号： H04L45/06
摘要： A router in which each of the input/output ports is associated with identifiers enabling each of the other input/output ports to locate it according to a code specific to each of them, comprising means for identifying in an incident packet a routing instruction indicating a forward identifier of the desired output port; and means for sending back the packet where the forward identifier is suppressed from the routing instruction and a return identifier is inserted therein.
摘要翻译：一种路由器，其中每个输入/输出端口与标识符相关联，使得每个其他输入/输出端口能够根据其中每个输入/输出端口的特定代码来定位它，包括用于在事件包中识别指示所需输出端口的正向标识符; 以及用于从所述路由指令发回所述前向标识符被抑制的分组并且在其中插入返回标识符的装置。

6. 发明授权

US11095308B2 Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes 有权
公开(公告)号：US11095308B2
公开(公告)日：2021-08-17
申请号：US16621956
申请日：2018-06-07
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Cédric Marchand , Emmanuel Boutillon
IPC分类号： H03M13/11
摘要： A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.

7. 发明申请

US20210250047A1 CHECK NODE PROCESSING METHODS AND DEVICES WITH INSERTION SORT 有权
公开(公告)号：US20210250047A1
公开(公告)日：2021-08-12
申请号：US17255101
申请日：2019-07-04
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Emmanuel BOUTILLON , Cédric MARCHAND , Hassan HARB
IPC分类号： H03M13/11
摘要： A sorting device for determining elementary check node components in an elementary check node processor (3) implemented in a non-binary error correcting code decoder by sorting auxiliary components. The auxiliary components are stored in a plurality of FIFO memories (33-n), each FIFO memory (33-n) being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory (33-n) comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory (33-n). The sorting device is configured to sort the auxiliary components by a plurality of multiplexers (34-m) arranged sequentially. Each multiplexers (34-m) is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the following steps: receive an auxiliary component extracted from the FIFO memory (33-n) which is assigned the FIFO number index comprised in the candidate elementary check node component determined at the previous iteration which comprises the most reliable candidate symbol, and update the candidate elementary check node component determined at the previous iteration by selecting one component among the received auxiliary component, the candidate elementary check node component determined at the previous iteration by the multiplexer (34-m), and the candidate elementary check node component determined at the previous iteration by the subsequent multiplexer (34-(m+1)). The sorting device is configured to determine, at each of the one or more iterations, an elementary check node component by selecting the candidate elementary check node component which comprises the most reliable candidate symbol.

8. 发明授权

US10476523B2 Elementary check node-based syndrome decoding using pre-sorted inputs 有权
公开(公告)号：US10476523B2
公开(公告)日：2019-11-12
申请号：US15723813
申请日：2017-10-03
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Cédric Marchand , Emmanuel Boutillon
IPC分类号： H03M13/11 , H04L1/00
摘要： At least a method and an apparatus are presented for decoding a signal. For example, a decoder is presented for determining an estimate of an encoded signal. The decoder comprises one or more variable node processing units and one or more check node processing units configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with the symbol. The at least one check processing unit is further configured to calculate at two or more elementary check node processors a set of syndromes from at least three permuted messages, a syndrome comprising a binary vector; generate at least one check node message from the set of syndromes depending on the binary vector, and send the at least one check node message to a signal estimation unit.

9. 发明申请

US20180115323A1 ELEMENTARY CHECK NODE-BASED SYNDROME DECODING USING PRE-SORTED INPUTS 审中-公开
公开(公告)号：US20180115323A1
公开(公告)日：2018-04-26
申请号：US15723813
申请日：2017-10-03
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Cédric MARCHAND , Emmanuel BOUTILLON
IPC分类号： H03M13/11
CPC分类号： H03M13/1131 , H03M13/1117 , H03M13/1128 , H03M13/1171 , H04L1/0041
摘要： Embodiments of the invention provide a decoder for determining an estimate of an encoded signal, the decoder comprising one or more variable node processing units (23) and one or more check node processing units (25) configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with said symbol, wherein the decoder comprises: at least one vector permutation unit (24) configured to receive a set of at least three variable node messages comprising variable node components from at least one variable node processing unit and to generate permuted messages depending on a plurality of the reliability metrics comprised in said variable node components, the variable node messages being sorted according to an order of the reliability metrics; and at least one check node processing unit (25-1) configured to: calculate at two or more elementary check node processors (26) a set of syndromes from said at least three permuted messages, generate at least one check node message from said set of syndromes, and send said at least one check node message to a signal estimation unit (29).

10. 发明申请

US20180076830A1 ELEMENTARY CHECK NODE PROCESSING FOR SYNDROME COMPUTATION FOR NON-BINARY LDPC CODES DECODING 审中-公开
公开(公告)号：US20180076830A1
公开(公告)日：2018-03-15
申请号：US15694062
申请日：2017-09-01
申请人： UNIVERSITE DE BRETAGNE SUD
发明人： Cédric MARCHAND , Emmanuel BOUTILLON
IPC分类号： H03M13/11
CPC分类号： H03M13/1131 , H03M13/1117 , H03M13/1171 , H03M13/6552 , H03M13/6555
摘要： Embodiments of the invention provide a check node processing unit implemented in a decoder for decoding a signal, the check node processing unit being configured to receive at least three input messages and to generate at least one output message, wherein the check node processing unit comprises: a syndrome calculator (31) configured to determine a set of syndromes from said at least three input messages using at least two elementary check node processors (311), each syndrome comprising a symbol, a reliability metric associated with said symbol, and a binary vector; a decorrelation unit (33) configured to determine, in association with at least an output message, a set of candidate components from said set of syndromes, each candidate component comprising a symbol and a reliability metric associated with said symbol, said set of candidate components comprising one or more pairs of components comprising a same symbol; and a selection unit (35) configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with said at least an output message.

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