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1. 发明申请

US20190161345A1 DEPOSITION OF PROTECTIVE MATERIAL AT WAFER LEVEL IN FRONT END FOR EARLY STAGE PARTICLE AND MOISTURE PROTECTION 审中-公开
公开(公告)号：US20190161345A1
公开(公告)日：2019-05-30
申请号：US15827057
申请日：2017-11-30
申请人： Infineon Technologies AG
发明人： Florian BRANDL , Manfred FRIES , Franz-Peter KALZ
IPC分类号： B81C1/00 , H01L21/50 , H01L23/04 , H01L23/10 , B81B7/00
CPC分类号： B81C1/00285 , B29C35/02 , B81B7/0029 , B81B7/0038 , B81B7/0045 , B81B7/0051 , B81C1/00063 , B81C1/0019 , B81C1/00301 , B81C1/0038 , B81C1/00904 , H01L21/50 , H01L23/04 , H01L23/10 , H01L2924/16235
摘要： A semiconductor device and a method of manufacturing the same are provided such that a microelectromechanical systems (MEMS) element is protected at an early manufacturing stage. A method for protecting a MEMS element includes: providing at least one MEMS element, having a sensitive area, on a substrate; and depositing, prior to a package assembly process, a protective material over the sensitive area of the at least one MEMS element such that the sensitive area of at least one MEMS element is sealed from an external environment, where the protective material permits a sensor functionality of the at least one MEMS element.

2. 发明授权

US09968964B2 Coating method using particle alignment and particle coated substrate manufactured thereby 有权
公开(公告)号：US09968964B2
公开(公告)日：2018-05-15
申请号：US14372118
申请日：2013-11-27
申请人： AJOU UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
发明人： Jae Ho Kim , Hyo Sop Kim
IPC分类号： B05D3/12 , B05D7/02 , B81C1/00 , C09D1/00 , C09D125/06
CPC分类号： B05D3/12 , B05D7/02 , B81C1/00031 , B81C1/0038 , C09D1/00 , C09D125/06 , Y10T428/24612
摘要： Disclosed is a coating method using particle alignment, including preparing a cohesive polymer substrate having a smooth surface; and coating the smooth surface of the cohesive polymer substrate with a plurality of particles while forming recesses respectively corresponding to the particles on the smooth surface of the cohesive polymer substrate by pressing the particles to the cohesive polymer substrate, so that binding properties between the particles and the cohesive polymer substrate are enhanced.

3. 发明申请

US20170197822A1 MEMBRANE TRANSDUCER STRUCTURES AND METHODS OF MANUFACTURING SAME USING THIN-FILM ENCAPSULATION 审中-公开
公开(公告)号：US20170197822A1
公开(公告)日：2017-07-13
申请号：US15469393
申请日：2017-03-24
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Emmanuel P. Quevy , Jeremy R. Hui , Carrie Wing-Zin Low
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
摘要： Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.

4. 发明授权

US09637371B2 Membrane transducer structures and methods of manufacturing same using thin-film encapsulation 有权
公开(公告)号：US09637371B2
公开(公告)日：2017-05-02
申请号：US14532675
申请日：2014-11-04
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Emmanuel P Quevy , Jeremy R. Hui , Carrie Wing-Zin Low
IPC分类号： B81B3/00 , B81B7/00 , B81C1/00 , G01N27/22
CPC分类号： B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
摘要： Membrane transducer structures and thin-film encapsulation methods for manufacturing the same are provided. In one example, the thin film encapsulation methods may be implemented to co-integrate processes for thin-film encapsulation and formation of microelectronic devices and microelectromechanical systems (MEMS) that include the membrane transducers.

5. 发明授权

US09550666B2 MEMS device with release aperture 有权
标题翻译：具有释放孔径的MEMS器件
公开(公告)号：US09550666B2
公开(公告)日：2017-01-24
申请号：US14613740
申请日：2015-02-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chung-Hsien Lin , Chia-Hua Chu , Chun-Wen Cheng
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81B7/0058 , B81C1/00333 , B81C1/0038 , B81C2203/0136 , B81C2203/0145 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a micro-electro-mechanical systems (MEMS) device. In an embodiment, a device includes a substrate; a MEMS structure disposed above a sacrificial layer opening above the substrate; a release aperture disposed at substantially a same level above the sacrificial layer opening as the MEMS structure; a first cap over the MEMS structure and the sacrificial layer opening, a leg of the first cap disposed between the MEMS structure and the release aperture; and a second cap plugging the release aperture.
摘要翻译：本公开提供了一种微机电系统（MEMS）装置。在一个实施例中，装置包括基板; 设置在所述衬底上方的牺牲层开口上方的MEMS结构; 释放孔，设置在与所述MEMS结构相似的牺牲层开口上方的基本相同的水平处; MEMS结构和牺牲层开口上的第一盖，设置在MEMS结构和释放孔之间的第一盖的腿; 以及封闭释放孔的第二帽。

6. 发明授权

US09512532B2 Methods of and apparatus for electrochemically fabricating structures via interlaced layers or via selective etching and filling of voids 有权
公开(公告)号：US09512532B2
公开(公告)日：2016-12-06
申请号：US14065720
申请日：2013-10-29
申请人： Microfabrica Inc.
发明人： Dennis R. Smalley
IPC分类号： C25D5/02 , B81C1/00 , G01P15/08 , G01P15/125 , H01L21/288 , H01L21/768 , H01P1/202 , H01P3/06 , H01P5/18 , H01P11/00 , C25D1/00 , C23C18/16 , G06F17/50 , H05K3/46
CPC分类号： C25D5/02 , B33Y10/00 , B33Y50/00 , B33Y50/02 , B81B2201/042 , B81C1/00126 , B81C1/0038 , C23C18/1605 , C23C18/1651 , C25D1/003 , G01P15/0802 , G01P15/125 , G06F17/5072 , H01L21/2885 , H01L21/76885 , H01P1/202 , H01P3/06 , H01P5/183 , H01P11/00 , H01P11/005 , H05K3/4647
摘要： Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.

7. 发明授权

US09422149B2 Trapped sacrificial structures and methods of manufacturing same using thin-film encapsulation 有权
标题翻译：捕获的牺牲结构和使用薄膜封装制造相同的方法
公开(公告)号：US09422149B2
公开(公告)日：2016-08-23
申请号：US14532723
申请日：2014-11-04
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Emmanuel P. Quevy , Louis Nervegna , Jeremy R. Hui
IPC分类号： B81B3/00 , B81B7/00 , B81C1/00 , G01N27/22
CPC分类号： B81C1/00246 , B81B3/0021 , B81B7/007 , B81B7/0077 , B81B7/008 , B81B2201/0214 , B81B2201/0235 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C1/00269 , B81C1/00285 , B81C1/00333 , B81C1/0038 , B81C2201/0105 , B81C2201/056 , B81C2203/0118 , B81C2203/0136 , B81C2203/0172 , B81C2203/019 , B81C2203/0735 , G01N27/223 , G01N27/227
摘要： Trapped sacrificial structures and thin-film encapsulation methods that may be implemented to manufacture trapped sacrificial structures such as relative humidity sensor structures, and spacer structures that protect adjacent semiconductor structures extending above a semiconductor die substrate from being contacted by a molding tool or other semiconductor processing tool in an area of a die substrate adjacent the spacer structures.
摘要翻译：捕获的牺牲结构和薄膜封装方法可用于制造捕获的牺牲结构，例如相对湿度传感器结构，以及保护在半导体管芯基板之上延伸的相邻半导体结构不被模具或其它半导体加工件接触的间隔结构工具在与衬垫结构相邻的管芯衬底的区域中。

8. 发明申请

US20150321908A1 DIELECTRIC POLYURETHANE FILM 有权
标题翻译：电介质聚氨酯薄膜
公开(公告)号：US20150321908A1
公开(公告)日：2015-11-12
申请号：US14410178
申请日：2013-06-24
申请人： Bayer MaterialScience AG
发明人： Joachim WAGNER , Jens KRAUSE , Dennis HONEL
IPC分类号： B81C1/00 , B81B3/00 , B29C39/00 , H01B3/30 , B32B27/40
CPC分类号： B81C1/0038 , B29C39/003 , B29K2075/00 , B29K2995/0006 , B29L2007/008 , B32B27/40 , B32B2250/03 , B32B2307/204 , B32B2457/00 , B81B3/0021 , C08G18/4211 , C08G18/44 , C08G18/7831 , C08J5/18 , C08J2375/04 , H01B3/302 , H01L41/193 , H01L41/45 , Y10T29/43 , Y10T428/31551
摘要： The present invention relates to a process for producing a dielectric polyurethane film, in which at least the following steps are performed continuously: I) a mixture comprising: a) a compound containing isocyanate groups and having a content of isocyanate groups of >10% by weight and ≦50% by weight, b) a compound containing isocyanate-reactive groups and having an OH number of ≧20 and ≦150, at least one solvent having a vapour pressure at 20° C. of >0.1 mbar and
摘要翻译：本发明涉及电介质聚氨酯薄膜的制造方法，其中至少连续进行以下步骤：I）混合物，其包含：a）含有异氰酸酯基的化合物，异氰酸酯基含量为> 10％以上的化合物重量和重量％; 50％重量，b）含有异氰酸酯反应性基团并且具有OH值≥20且≥N1E的化合物; 150，至少一种蒸气压在20℃下> 0.1毫巴和< 200mbar，产生至少一种润湿添加剂，其中化合物a）和b）中异氰酸酯基团和异氰酸酯反应性基团的数均官能度的总和为2.6并且＆nlE; 6，II）紧随其后将该混合物以湿膜形式施加到载体上，III）湿膜固化形成聚氨酯膜，IV）将聚氨酯膜与载体分离。本发明还提供了可通过本发明的方法获得的电介质聚氨酯膜，用于制造机电换能器的方法，以及可通过该方法获得的机电换能器。

9. 发明申请

US20150274507A1 MEMS DEVICE AND FORMATION METHOD THEREOF 有权
标题翻译： MEMS器件及其形成方法
公开(公告)号：US20150274507A1
公开(公告)日：2015-10-01
申请号：US14645741
申请日：2015-03-12
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： WEI XU , GUOAN LIU
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81B7/007 , B81B7/02 , B81B2201/0235 , B81B2201/0264 , B81B2207/07 , B81B2207/096 , B81C1/0038 , B81C2203/01 , G01L9/0042 , G01P15/0802 , G01P15/125
摘要： The present disclosure provides MEMS devices and their fabrication methods. A first dielectric layer is formed on a substrate including integrated circuits therein. One or more first metal connections and second metal connections are formed in the first dielectric layer and are electrically connected to the integrated circuits. A second dielectric layer is formed on the first dielectric layer. An acceleration sensor is formed in the second dielectric layer to electrically connect to the one or more first metal connections. One or more first metal vias are formed in the second dielectric layer to electrically connect to the second metal connections. A pressure sensor is formed on the second dielectric layer to electrically connect to the first metal vias. The MEMS devices provided by the present disclosure are compact in size through the integration of the acceleration sensor and the pressure sensor.
摘要翻译：本公开提供了MEMS器件及其制造方法。在其上包括集成电路的基板上形成第一电介质层。一个或多个第一金属连接和第二金属连接形成在第一电介质层中并且电连接到集成电路。在第一电介质层上形成第二电介质层。加速度传感器形成在第二电介质层中以电连接到一个或多个第一金属连接。一个或多个第一金属通孔形成在第二电介质层中以电连接到第二金属连接。压力传感器形成在第二电介质层上以电连接到第一金属通孔。由本公开提供的MEMS装置通过加速度传感器和压力传感器的集成而尺寸紧凑。

10. 发明授权

US09102518B2 Process for modifying the properties of a thin layer and substrate applying said process 有权
标题翻译：用于改变施加所述方法的薄层和底物的性质的方法
公开(公告)号：US09102518B2
公开(公告)日：2015-08-11
申请号：US12470540
申请日：2009-05-22
申请人： Olivier Marty , Volodymyr Lysenko
发明人： Olivier Marty , Volodymyr Lysenko
IPC分类号： H01L29/02 , B81C1/00 , H01L21/02 , C30B25/02 , H01L39/24 , H01L41/332
CPC分类号： B81C1/0038 , B81C1/00714 , C30B25/02 , H01L21/0237 , H01L21/02381 , H01L21/02439 , H01L21/02463 , H01L21/02513 , H01L21/02521 , H01L21/02543 , H01L21/02546 , H01L21/0259 , H01L21/02658 , H01L39/2454 , H01L41/332 , Y10S977/72 , Y10S977/811 , Y10S977/825 , Y10S977/832 , Y10T428/24802
摘要： The invention relates to a process for modifying the properties of a thin layer (1) formed on the surface of a support (2) forming a substrate (3) utilized in the field of microelectronics, nanoelectronics or microtechnology, nanotechnology, characterized in that it consists of: forming at least one thin layer (1) on a nanostructured support with high specific surface (2), and treating the nanostructured support with high specific surface (2) to generate internal strains in the support causing its deformation at least in the plane of the thin layer so as to ensure corresponding deformation of the thin layer to modify its properties.
摘要翻译：本发明涉及一种用于改变在微电子学，纳米电子学或微技术领域中使用的形成衬底（3）的支撑体（2）的表面上形成的薄层（1）的性质的方法，其特征在于它包括：在具有高比表面积（2）的纳米结构化载体上形成至少一个薄层（1），以及用高比表面积（2）处理纳米结构的载体以在载体中产生至少在平面，以确保薄层的相应变形，以改变其性能。

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