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    • 9. 发明授权
    • Method for atomic layer deposition
    • 原子层沉积方法
    • US09506144B2
    • 2016-11-29
    • US13487702
    • 2012-06-04
    • Ching-Shun KuHsin-Yi Lee
    • Ching-Shun KuHsin-Yi Lee
    • C23C16/00C23C16/40C23C16/455
    • C23C16/407C23C16/45525C23C16/45527C23C16/45529C23C16/45531C23C16/45534
    • A method for atomic layer deposition includes providing a substrate in a reaction chamber; and performing at least one atomic layer deposition cycle to form a film on a surface of the substrate. The atomic layer deposition cycle includes passing first precursors into the reaction chamber to let first atoms included in the first precursors combine with reaction sites of the substrate; and passing second precursors into the reaction chamber to let second atoms included in the second precursors combine with the reaction sites uncombined with the first atoms or substitute at least part of the first atoms to combine with the reaction sites of the substrate. The above-mentioned method for atomic layer deposition is capable of preparing large area and uniformity of doping film without annealing process or with low temperature annealing process.
    • 原子层沉积的方法包括在反应室中提供衬底; 以及执行至少一个原子层沉积循环以在所述衬底的表面上形成膜。 原子层沉积循环包括使第一前体进入反应室以使包含在第一前体中的第一个原子与底物的反应位点相结合; 并将第二前体通入反应室以使包含在第二前体中的第二个原子与未与第一个原子结合的反应位点结合,或者将至少部分第一个原子取代与底物的反应位点结合。 上述原子层沉积的方法能够在没有退火工艺或低温退火工艺的情况下制备掺杂膜的大面积和均匀性。
    • 10. 发明授权
    • Indium gallium zinc oxide layers for thin film transistors
    • 用于薄膜晶体管的铟镓锌氧化物层
    • US09502242B2
    • 2016-11-22
    • US14599696
    • 2015-01-19
    • Applied Materials, Inc.
    • Tae Kyung WonJohn M. WhiteSoo Young ChoiJung-Chi (Eric) Lu
    • H01L21/02C23C16/40C23C16/455C23C16/509
    • H01L21/02565C23C16/407C23C16/45574C23C16/5096H01L21/02472H01L21/02483H01L21/02554H01L21/0262H01L29/66969H01L29/7869H01L29/78693H01L29/78696
    • Embodiments of the present disclosure generally provide a method and apparatus for forming an IGZO active layer within a thin film transistor (TFT) device. In one embodiment, a method is provided for forming an IGZO active layer on a dielectric surface using a PECVD deposition process. In one embodiment, a method is provided for pretreating and passivating the dielectric surface for receiving the PECVD formed IGZO layer. In another embodiment, a method is provided for treating a PECVD formed IGZO layer after depositing said layer. In another embodiment, a method is provided for forming a multi-layer or complex layering structure of IGZO, within a PECVD processing chamber, for optimizing TFT electrical characteristics such as carrier density, contact resistance, and gate dielectric interfacial properties. In yet another embodiment, a method is provided for forming integrated layers for a TFT including IGZO within an in-situ environment of a cluster tool.
    • 本公开的实施例通常提供了用于在薄膜晶体管(TFT)器件内形成IGZO有源层的方法和装置。 在一个实施例中,提供了一种使用PECVD沉积工艺在电介质表面上形成IGZO有源层的方法。 在一个实施例中,提供了一种用于预处理和钝化用于接收形成PECVD的IGZO层的电介质表面的方法。 在另一个实施例中,提供了一种在沉积所述层之后处理形成的PECVD层的方法。 在另一个实施例中,提供了一种用于在PECVD处理室内形成IGZO的多层或复合分层结构的方法,用于优化诸如载流子密度,接触电阻和栅介质界面性质的TFT电特性。 在另一个实施例中,提供了一种用于在集群工具的原位环境内形成用于包括IGZO的TFT的集成层的方法。