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1. 发明申请

US20180059183A1 SEMICONDUCTOR DEVICE AND SCAN TEST METHOD 审中-公开
公开(公告)号：US20180059183A1
公开(公告)日：2018-03-01
申请号：US15549624
申请日：2015-04-16
申请人： Renesas Electronics Corporation
发明人： Yoichi MAEDA , Jun MATSUSHIMA , Hiroki WADA
IPC分类号： G01R31/319 , G01R31/3185 , G01R31/3193 , G06F11/267
CPC分类号： G01R31/31921 , G01R31/318508 , G01R31/318516 , G01R31/318547 , G01R31/318594 , G01R31/31922 , G01R31/3193 , G06F11/267
摘要： A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

2. 发明申请

US20100306609A1 Low Power Decompression Of Test Cubes 有权
标题翻译：测试立方体的低功率减压
公开(公告)号：US20100306609A1
公开(公告)日：2010-12-02
申请号：US12854786
申请日：2010-08-11
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

3. 发明授权

US07797603B2 Low power decompression of test cubes 有权
标题翻译：测试立方体的低功率减压
公开(公告)号：US07797603B2
公开(公告)日：2010-09-14
申请号：US11880373
申请日：2007-07-19
申请人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
发明人： Janusz Rajski , Grzegorz Mrugalski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/28
CPC分类号： G01R31/31921 , G01R31/318335
摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.
摘要翻译：以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

4. 发明申请

US20100229060A1 Compression Based On Deterministic Vector Clustering Of Incompatible Test Cubes 有权
标题翻译：基于不相容性测试立方体的确定性矢量聚类的压缩
公开(公告)号：US20100229060A1
公开(公告)日：2010-09-09
申请号：US12718813
申请日：2010-03-05
申请人： GRZEGORZ MRUGALSKI , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
发明人： GRZEGORZ MRUGALSKI , Nilanjan Mukherjee , Janusz Rajski , Dariusz Czysz , Jerzy Tyszer
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921 , G01R31/318547
摘要： The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.
摘要翻译：测试数据压缩方案基于确定性向量聚类。在存在冲突的情况下，具有许多类似指定位的测试立方体将合并到父模式中。父模式以及表示冲突位的控制模式和增量模式被有效地编码。三模式解压缩器可用于解压缩测试数据。

5. 发明申请

US20100171509A1 CHIP TESTING CIRCUIT 有权
标题翻译：芯片测试电路
公开(公告)号：US20100171509A1
公开(公告)日：2010-07-08
申请号：US12548828
申请日：2009-08-27
申请人： Der-Min YUAN , Ming-Cheng Liang , Kuo-Hua Lee
发明人： Der-Min YUAN , Ming-Cheng Liang , Kuo-Hua Lee
IPC分类号： G01R31/02
CPC分类号： G01R31/31921 , G11C29/40
摘要： The invention discloses a chip testing circuit that increases the testing throughput. The chip testing circuit uses a multiplexer to switch the connection of the data compressing circuit between data compressing base units which compress 4 XIOs, so as to obtain a multiplexer of testing data by one single interface circuit and to increase the testing throughput.
摘要翻译：本发明公开了一种提高测试吞吐量的芯片测试电路。芯片测试电路使用多路复用器在数据压缩基础单元之间切换数据压缩电路的连接，压缩基站单元压缩4个XIO，以便通过单个接口电路获得测试数据的多路复用器，并提高测试吞吐量。

6. 发明申请

US20090249147A1 FAULT DIAGNOSIS OF COMPRESSED TEST RESPONSES 有权
标题翻译：压力测试反应的故障诊断
公开(公告)号：US20090249147A1
公开(公告)日：2009-10-01
申请号：US12405828
申请日：2009-03-17
申请人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
发明人： Janusz Rajski , Grzegorz Mrugalski , Artur Pogiel , Jerzy Tyszer , Chen Wang
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/318547 , G01R31/31703 , G01R31/318536 , G01R31/318566 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.
摘要翻译：本文公开了用于诊断来自压缩测试响应的故障扫描单元的方法，装置和系统。例如，在一个非限制性示例性实施例中，接收到包括多个比特（包括一个或多个错误比特）的至少一个错误签名。使用搜索树来评估多个潜在错误位解释扫描单元候选。确定所评估的扫描单元候选中的一个或多个是否解释错误签名中的错误位，从而构成一个或多个故障扫描单元。由确定的任何这样的一个或多个故障扫描单元提供输出。还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的有形计算机可读介质。还提供了包括由任何所公开的方法识别的故障扫描单元的列表的有形计算机可读介质。

7. 发明授权

US07559000B2 Integrated circuit device, diagnosis method and diagnosis circuit for the same 有权
标题翻译：集成电路器件，诊断方法和诊断电路相同
公开(公告)号：US07559000B2
公开(公告)日：2009-07-07
申请号：US11402049
申请日：2006-04-12
申请人： Tsutomu Sato
发明人： Tsutomu Sato
IPC分类号： G01R31/3183 , G01R31/40
CPC分类号： G01R31/31921 , G01R31/31919
摘要： Hardware diagnosis of a disk array apparatus is conducted before shipment by using a self-diagnosis circuit, using the same criteria that apply to actual in-use equipment. A logical circuit and a self-diagnosis circuit are mounted on an LSI. When a test program is loaded to a RAM and a diagnosis command is input to a CPU before shipment, a pattern generation circuit generates a pattern and expected value pattern data corresponding to the pattern under the control of the CPU. When the pattern is input to the logical circuit, the logical circuit operates according to the pattern and outputs pattern data showing the test result. An expected value checking circuit compares and checks this pattern data against the expected value pattern data and then outputs the diagnosis result regarding whether the logical circuit is normal or abnormal. The content of the diagnosis result is displayed on an external display unit.
摘要翻译：磁盘阵列装置的硬件诊断是通过使用自诊断电路在出货前进行的，使用与实际使用中的设备相同的标准。逻辑电路和自诊断电路安装在LSI上。当测试程序被加载到RAM并且在出货之前向CPU输入诊断命令时，模式产生电路在CPU的控制下产生对应于模式的模式和期望值模式数据。当图案被输入到逻辑电路时，逻辑电路根据图案进行操作并输出表示测试结果的图形数据。期望值检查电路将该图案数据与期望值图案数据进行比较并检查，然后输出关于逻辑电路是正常还是异常的诊断结果。诊断结果的内容显示在外部显示单元上。

8. 发明申请

US20090119556A1 METHOD AND APPARATUS FOR TESTING LOGIC CIRCUIT DESIGNS 失效
标题翻译：用于测试逻辑电路设计的方法和装置
公开(公告)号：US20090119556A1
公开(公告)日：2009-05-07
申请号：US12265330
申请日：2008-11-05
申请人： Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
发明人： Kedarnath Balakrishnan , Seongmoon Wang , Wenlong Wei , Srimat T. Chakradhar
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/31921
摘要： Disclosed is a logic testing system that includes a decompressor and a tester in communication with the decompressor. The tester is configured to store a seed and locations of scan inputs and is further configured to transmit the seed and the locations of scan inputs to the decompressor. The decompressor is configured to generate a test pattern from the seed and the locations of scan inputs. The decompressor includes a first test pattern generator, a second test pattern generator, and a selector configured to select the test pattern generated by the first test pattern generator or the test pattern generated by the second test pattern generator using the locations of scan inputs.
摘要翻译：公开了一种包括解压缩器和与解压缩器通信的测试器的逻辑测试系统。测试器被配置为存储种子和扫描输入的位置，并且还被配置为将种子和扫描输入的位置传送到解压缩器。解压缩器被配置为从种子和扫描输入的位置生成测试图案。解压缩器包括第一测试图案发生器，第二测试图案发生器和被配置为选择由第一测试图案发生器生成的测试图案或由第二测试图案发生器使用扫描输入位置产生的测试图案的选择器。

9. 发明授权

US07516381B2 Integrated circuit test system 失效
标题翻译：集成电路测试系统
公开(公告)号：US07516381B2
公开(公告)日：2009-04-07
申请号：US11407928
申请日：2006-04-21
申请人： Yoji Masuda
发明人： Yoji Masuda
IPC分类号： G01R31/28
CPC分类号： G01R31/31921
摘要： A test pattern compressed by an algorithm allowing real-time expansion of data corresponding to each of pins of an LSI is stored in a pattern memory of a pattern generator. A frame processor executes a predetermined program to perform expansion of a test pattern output by the pattern generator by software, generates, based on expanded data, a pulse waveform, and outputs the generated pulse waveform.
摘要翻译：通过允许对应于LSI的每个引脚的数据的实时扩展的算法压缩的测试图案被存储在模式发生器的模式存储器中。帧处理器执行预定程序以通过软件执行由模式发生器输出的测试模式的扩展，基于扩展数据生成脉冲波形，并输出所生成的脉冲波形。

10. 发明授权

US07444271B2 Scoring mechanism for automatically generated test programs 有权
标题翻译：自动生成测试程序的评分机制
公开(公告)号：US07444271B2
公开(公告)日：2008-10-28
申请号：US11002991
申请日：2004-12-03
申请人： Simon John Craske , Eric Jason Furbish , Jonathan William Brawn
发明人： Simon John Craske , Eric Jason Furbish , Jonathan William Brawn
IPC分类号： G06F17/50 , G06N3/00 , G06F11/36
CPC分类号： G01R31/318307 , G01R31/31919 , G01R31/31921
摘要： A test program for a data processing apparatus is produced using a genetic algorithm which mutates instances being ordered lists of program instructions within a population forming the test program. The populations are evaluated using a metric by which the population as a whole is scored for its stimulation of predetermined functional points within the data processing apparatus when a determination is being made as to whether or not a particular instance should be swapped in or out of the population.
摘要翻译：使用遗传算法来生成数据处理装置的测试程序，所述遗传算法在形成测试程序的群体中将实例作为程序指令的有序列表进行变化。使用一个度量来评估群体，当一个度量决定了特定实例是否应被交换到或从该数据处理设备中进行调整时人口。

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