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1. 发明授权

US09379727B1 Transmit digital to analog converter (DAC) spur attenuation 有权
标题翻译：发送数模转换器（DAC）杂散衰减
公开(公告)号：US09379727B1
公开(公告)日：2016-06-28
申请号：US14628996
申请日：2015-02-23
申请人： QUALCOMM Incorporated
发明人： Dongwon Seo , Yang You , Honghao Ji , Tongyu Song , Ganesh Saripalli , Shahin Mehdizad Taleie
IPC分类号： H03M1/06 , H03M1/70 , H04B1/04 , G05F3/18 , G05F1/56 , H03M1/00 , H03M1/74 , G05F1/575 , H02M3/156
CPC分类号： H03M1/0604 , G05F1/56 , G05F1/575 , G05F3/18 , H02M3/156 , H03F3/24 , H03M1/00 , H03M1/70 , H03M1/747 , H04B1/0475 , H04B2001/0408
摘要： A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.
摘要翻译：提供了用于衰减发射数模转换器（DAC）杂散的方法和装置。当将参考电压注入放大器时，该方法开始。接下来，测量接地低压降稳压器的输出，并将其与参考电压进行比较。然后根据比较结果调整放大器的输出。如果参考电压较高，则接地低压降稳压器的输出将放大器的输出调整到地。如果参考电压低于接地低压降稳压器的输出，则调节放大器的输出以匹配参考电压。

2. 发明申请

US20160181800A1 Stacked Power Supply for Reduced Current Consumption 审中-公开
标题翻译：堆叠电源降低电流消耗
公开(公告)号：US20160181800A1
公开(公告)日：2016-06-23
申请号：US14799638
申请日：2015-07-15
申请人： Dialog Semiconductor (UK) Limited
发明人： Horst Knoedgen
IPC分类号： H02J1/10
CPC分类号： G05F3/26 , G05F1/577 , G05F3/16 , G05F3/18
摘要： A circuit arrangement comprising a first capacitor and a second capacitor which are arranged in series between a high potential and a low potential is described. The circuit arrangement comprises first power consuming circuitry which is arranged in parallel to the first capacitor. The first power consuming circuitry (113) consumes electrical power at a first voltage. The circuit arrangement comprises second power consuming circuitry which is arranged in parallel to the second capacitor . The second power consuming circuitry consumes electrical power at a second voltage, wherein a magnitude of the sum of the first voltage and the second voltage is smaller than an absolute difference between the high potential and the low potential. The circuit arrangement sets a voltage at the first capacitor in accordance to the first voltage and to set a voltage at the second capacitor in accordance to the second voltage.
摘要翻译：描述了包括串联设置在高电位和低电位之间的第一电容器和第二电容器的电路装置。电路装置包括与第一电容器并联布置的第一功耗电路。第一电力消耗电路（113）在第一电压下消耗电力。电路装置包括与第二电容器并联布置的第二电力消耗电路。第二功率消耗电路在第二电压下消耗电力，其中第一电压和第二电压之和的大小小于高电位和低电位之间的绝对差。电路装置根据第一电压设置第一电容器处的电压，并根据第二电压设置第二电容器处的电压。

3. 发明申请

US20160091917A1 CONSTANT CURRENT-CONSTANT VOLTAGE CIRCUIT 审中-公开
标题翻译：恒定电流恒定电路
公开(公告)号：US20160091917A1
公开(公告)日：2016-03-31
申请号：US14891743
申请日：2014-06-17
申请人： DENSO CORPORATION
发明人： Takashi IMURA
IPC分类号： G05F3/26
CPC分类号： G05F3/262 , G05F3/18 , G05F3/24
摘要： A constant current-constant voltage circuit includes a first resistor; a first transistor that is an N-channel type; a second transistor; a third transistor that is a P-channel type; a fourth transistor that is a P-channel type; a fifth transistor; a second resistor; and a first constant voltage element. The second resistor is coupled between the intermediate node and a source of the third transistor and the first constant voltage element is coupled between a source of the second transistor and the second power source line. A bias is set up and a source potential of the first transistor is equal to a source potential of the fifth transistor.
摘要翻译：恒定电流恒压电路包括第一电阻器; 第一晶体管是N沟道型; 第二晶体管; 第三晶体管是P沟道型; 第四晶体管是P沟道型; 第五晶体管; 第二电阻器; 和第一恒压元件。第二电阻器耦合在中间节点和第三晶体管的源极之间，第一恒压元件耦合在第二晶体管的源极和第二电源线之间。建立偏置，并且第一晶体管的源极电位等于第五晶体管的源极电位。

4. 发明申请

US20150370279A1 REFERENCE VOLTAGE CIRCUIT 有权
标题翻译：参考电压电路
公开(公告)号：US20150370279A1
公开(公告)日：2015-12-24
申请号：US14842179
申请日：2015-09-01
申请人： FUJI ELECTRIC CO., LTD.
发明人： Masashi AKAHANE
IPC分类号： G05F3/18
CPC分类号： G05F3/185 , G05F3/18
摘要： A reference voltage circuit including a constant voltage circuit and a resistance voltage divider circuit. The constant voltage circuit includes a Zener diode, and a bias current circuit connected in series with the Zener diode and causing a constant current to flow into the Zener diode. The resistance voltage divider circuit is connected in parallel with the Zener diode, and includes first and second resistors connected in series. The first resistor is connected to a cathode side of the Zener diode, and is formed of a low temperature coefficient resistor body that is temperature-independent. The second resistor is connected to an anode side of the Zener diode, and is formed of a resistor body having temperature characteristics that are the reverse of output temperature characteristics of the Zener diode.
摘要翻译：一种参考电压电路，包括恒压电路和电阻分压电路。恒压电路包括齐纳二极管和与齐纳二极管串联连接并使恒定电流流入齐纳二极管的偏置电流电路。电阻分压器电路与齐纳二极管并联连接，并包括串联连接的第一和第二电阻器。第一个电阻连接到齐纳二极管的阴极侧，由与温度无关的低温系数电阻体构成。第二电阻器连接到齐纳二极管的阳极侧，并且由具有与齐纳二极管的输出温度特性相反的温度特性的电阻体构成。

5. 发明授权

US09158320B1 Methods and apparatus for low input voltage bandgap reference architecture and circuits 有权
标题翻译：低输入电压带隙参考架构和电路的方法和装置
公开(公告)号：US09158320B1
公开(公告)日：2015-10-13
申请号：US14454342
申请日：2014-08-07
申请人： PsiKick, Inc.
发明人： Aatmesh Shrivastava
IPC分类号： G05F3/30 , G05F1/46 , G05F3/18
CPC分类号： G05F1/468 , G05F3/18 , G05F3/30
摘要： In some embodiments, an apparatus includes a bandgap reference circuit having a first bipolar junction transistor (BJT) that can receive a current from a node having a terminal voltage and can output a base emitter voltage. The apparatus also includes a second bipolar junction transistor (BJT) having a device width greater than a device width of the first BJT. The second BJT can receive a current from a node having a terminal voltage and output a base emitter voltage. In such embodiments, the apparatus also includes a reference generation circuit operatively coupled to the first BJT and the second BJT, where the reference generation circuit can generate a bandgap reference voltage based on the base emitter voltage of the first BJT and the base emitter voltage of the second BJT.
摘要翻译：在一些实施例中，一种装置包括具有第一双极结型晶体管（BJT）的带隙基准电路，该第一双极结型晶体管可以从具有端子电压的节点接收电流，并可输出基极发射极电压。该装置还包括具有大于第一BJT的器件宽度的器件宽度的第二双极结型晶体管（BJT）。第二BJT可以从具有端电压的节点接收电流并输出基极发射极电压。在这样的实施例中，该装置还包括可操作地耦合到第一BJT和第二BJT的参考产生电路，其中参考生成电路可以基于第一BJT的基极发射极电压和基极发射极电压产生带隙参考电压第二个BJT。

6. 发明申请

US20120075895A1 Universal-Voltage Discrete Input Circuit 有权
标题翻译：通用电压离散输入电路
公开(公告)号：US20120075895A1
公开(公告)日：2012-03-29
申请号：US13213625
申请日：2011-08-19
申请人： Daniel Rian Kletti , Timothy Mark Kromrey
发明人： Daniel Rian Kletti , Timothy Mark Kromrey
IPC分类号： H02M7/06 , G05F3/16
CPC分类号： G05F3/18
摘要： A universal-voltage discrete input circuit uses a high voltage depletion-mode field effect transistor in combination with a low-voltage, adjustable precision shunt regulator and an isolation circuit for interfacing a low voltage digital logic circuit to a switched external voltage ranging from about 7 volts to about 1000 volts AC or +/−DC, at a low fixed current. In addition to the wide input voltage range accepted at a uniform low current value, very high voltage isolation is provided between the external voltage and the low voltage digital logic circuit, and elimination of ground loops and common mode noise.
摘要翻译：通用电压离散输入电路使用高电压耗尽型场效应晶体管与低压，可调精密并联稳压器和隔离电路组合，用于将低压数字逻辑电路与约7的开关外部电压伏特到大约1000伏交流或+/-直流，固定电流较低。除了在均匀的低电流值下接受的宽输入电压范围外，在外部电压和低压数字逻辑电路之间提供非常高的电压隔离，并消除接地回路和共模噪声。

7. 发明授权

US07423416B1 Voltage regulator and method for providing a regulated output 有权
标题翻译：稳压器和提供稳压输出的方法
公开(公告)号：US07423416B1
公开(公告)日：2008-09-09
申请号：US11853939
申请日：2007-09-12
申请人： Bryan Quinones , William E. Edwards , Randall C. Gray
发明人： Bryan Quinones , William E. Edwards , Randall C. Gray
IPC分类号： G05F3/16
CPC分类号： G05F3/18
摘要： A voltage regulator includes first and second MOS transistors and a bipolar transistor. The first MOS transistor has a first conductivity type and has a drain coupled to a first power supply voltage terminal, a gate for receiving a first bias voltage, and a source. The second MOS transistor has a second conductivity type and has a source coupled to the first power supply voltage terminal, a drain coupled to the source of the first MOS transistor, and a gate for receiving a second bias voltage. The bipolar transistor has a collector coupled to the source of the first MOS transistor, a base for receiving a third bias voltage, and an emitter for providing an output voltage. The first MOS transistor and the second MOS transistor control a voltage level at the collector of the bipolar transistor in response to a varying power supply voltage provided to the first power supply voltage terminal.
摘要翻译：电压调节器包括第一和第二MOS晶体管和双极晶体管。第一MOS晶体管具有第一导电类型，并且具有耦合到第一电源电压端子的漏极，用于接收第一偏置电压的栅极和源极。第二MOS晶体管具有第二导电类型，并且具有耦合到第一电源电压端子的源极，耦合到第一MOS晶体管的源极的漏极和用于接收第二偏置电压的栅极。双极晶体管具有耦合到第一MOS晶体管的源极的集电极，用于接收第三偏置电压的基极和用于提供输出电压的发射极。第一MOS晶体管和第二MOS晶体管响应于提供给第一电源电压端子的变化的电源电压而控制双极晶体管的集电极处的电压电平。

8. 发明申请

US20060239048A1 Circuit and method for reducing the size and cost of switch-mode power supplies 有权
标题翻译：用于减小开关电源的尺寸和成本的电路和方法
公开(公告)号：US20060239048A1
公开(公告)日：2006-10-26
申请号：US11111138
申请日：2005-04-21
申请人： Michael Carter
发明人： Michael Carter
IPC分类号： H02M7/00
CPC分类号： G05F3/18 , H02M3/156
摘要： An improved circuit and method for decreasing the size and cost of switch mode power supplies is disclosed. In one illustrative example, a feedback circuit for a switch mode power supply is disclosed that includes two error amplifiers. The input of a first error amplifier is coupled to a voltage source associated with a load for the supply, and the input of a second error amplifier is coupled to a current source also associated with the load for the supply. Each one of the error amplifiers includes an adjustable shunt regulator that functions as an amplifier stage and diode. Also, the outputs of the. shunt regulators are connected together. Therefore, the shunt regulator of the first error amplifier can be used to select a voltage limit for the power supply, the shunt regulator of the second error amplifier can be used to select a current set point for the power supply, and the open collector functions of the shunt regulators serve to OR the output signals from the two error amplifiers to produce a signal indicating the loading of the supply. In this manner, an improved feedback circuit for a switch mode power supply is provided that performs the same functions as prior feedback circuits, but has at least three less discrete components (e.g., two diodes and a voltage reference) than the prior feedback circuits. Thus, the disclosed feedback circuit significantly reduces both the size and cost of switch mode power supplies.
摘要翻译：公开了一种用于减小开关电源的尺寸和成本的改进的电路和方法。在一个说明性示例中，公开了一种用于开关模式电源的反馈电路，其包括两个误差放大器。第一误差放大器的输入耦合到与用于电源的负载相关联的电压源，并且第二误差放大器的输入耦合到也与用于电源的负载相关联的电流源。每个误差放大器都包括一个可调节分流调节器，用作放大器级和二极管。另外，输出的。并联稳压器连接在一起。因此，第一误差放大器的分流调节器可用于选择电源的电压限制，第二误差放大器的并联调节器可用于选择电源的当前设定点，开路集电极功能分流稳压器用于OR或来自两个误差放大器的输出信号以产生指示电源负载的信号。以这种方式，提供用于开关模式电源的改进的反馈电路，其执行与现有反馈电路相同的功能，但是具有比现有反馈电路至少三个较小的分立组件（例如，两个二极管和参考电压）。因此，所公开的反馈电路显着地降低了开关模式电源的尺寸和成本。

9. 发明授权

US06236547B1 Zener zapping device and zener zapping method 失效
标题翻译：齐纳切割装置和齐纳切割方法
公开(公告)号：US06236547B1
公开(公告)日：2001-05-22
申请号：US09352874
申请日：1999-07-13
申请人： Masahiro Yamamoto
发明人： Masahiro Yamamoto
IPC分类号： H02H900
CPC分类号： G05F3/18
摘要： An object of the invention is to obtain a Zener zapping device which can reduce the time required for Zener-zapping and the scale of the device. A voltage setting circuit has a terminal (1), a current source (2) having its one end grounded, a Zener diode (ZD, 6a) having its one end connected to the terminal (1) and the other end of the current source (2), a resistor (5a) having its one end connected to the terminal (1), a relay (7a) having its one end connected to the other end of the current source (2), a ZD (6b) having its one end connected to the other end of the resistor 5a, the other end of the ZD (6a), and the other end of the relay (7a), a resistor (5b) having its one end connected to the other end of the resistor (5a) and the other end of the ZD (6a), a relay (7b) having its one end connected to the other end of the ZD (6a) and the other end of the relay (7a), a ZD (6c) having its one end connected to the other end of the resistor (5b), the other end of the ZD (6b), and the other end of the relay (7b), and its other end grounded, a resistor (5c) having its one end connected to the other end of the resistor (5b) and the other end of the ZD (6b), and its other end grounded, and a relay (7c) having its one end connected to the other end of the ZD (6b) and the other end of the relay (7b), and its other end grounded.
摘要翻译：本发明的一个目的是获得一种可以减少齐纳切换所需时间和设备尺寸的齐纳切割装置。电压设定电路具有端子（1），其一端接地的电流源（2），其一端连接到端子（1）的齐纳二极管（ZD，6a）和电流源的另一端（2），其端部连接到端子（1）的电阻器（5a），其一端连接到电流源（2）的另一端的继电器（7a），具有其一端连接到电阻器5a的另一端，ZD（6a）的另一端和继电器（7a）的另一端，电阻器（5b）的一端连接到电阻器的另一端（5a）和ZD（6a）的另一端，其一端连接到ZD（6a）的另一端和继电器（7a）的另一端的继电器（7b），ZD（6c）其一端连接到电阻器（5b）的另一端，ZD（6b）的另一端和继电器（7b）的另一端，并且其另一端接地，电阻器（5c）具有其一端连接到电阻（5b）的另一端 ZD（6b）的另一端和另一端接地，并且其一端连接到ZD（6b）的另一端和继电器（7b）的另一端的继电器（7c）及其另一端端接地。

10. 发明授权

US6160439A Current feed control circuit and electronic appliance using the same 失效
标题翻译：电流馈电控制电路及使用其的电子设备
公开(公告)号：US6160439A
公开(公告)日：2000-12-12
申请号：US907457
申请日：1997-08-08
申请人： Taisuke Abe , Mitsuhiko Kikuoka , Kengo Matsuda , Masami Segawa
发明人： Taisuke Abe , Mitsuhiko Kikuoka , Kengo Matsuda , Masami Segawa
IPC分类号： G05F3/18 , H03K17/72
CPC分类号： G05F3/18
摘要： The constitution includes a heater 2 used as current receiving element, a thyristor 3 placed in the current travelling route of the heater 2, a series connection circuit of a capacitor 4 and diode 5 for control power source connected parallel to the thyristor 3, a Zener diode 9 as a constant voltage element connected to the gate of the thyristor 3, and a control circuit 6 connected parallel to the capacitor 4, with its control terminal connected to the gate of the thyristor 3, whereby a specified control voltage determined by the Zener voltage of the Zener diode 9 is obtained at the first capacitor 4 by the control of the thyristor 3, so that the transformer for stepping down the supply voltage is not necessary.
摘要翻译：该结构包括用作电流接收元件的加热器2，放置在加热器2的电流行进路径中的晶闸管3，电容器4的串联连接电路和用于与晶闸管3并联连接的控制电源的二极管5，齐纳二极管二极管9作为连接到晶闸管3的栅极的恒压元件，以及与电容器4并联连接的控制电路6，其控制端子连接到晶闸管3的栅极，由此由齐纳二极管确定的指定的控制电压通过晶闸管3的控制，在第一电容器4处获得齐纳二极管9的电压，从而不需要用于降低电源电压的变压器。

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