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1. 发明申请

US20160041947A1 IMPLEMENTING A SQUARE ROOT OPERATION IN A COMPUTER SYSTEM 有权
标题翻译：在计算机系统中实现方圆操作
公开(公告)号：US20160041947A1
公开(公告)日：2016-02-11
申请号：US14452358
申请日：2014-08-05
申请人： Imagination Technologies, Limited
发明人： Leonard Rarick
IPC分类号： G06F17/10
CPC分类号： G06F7/5525 , G06F2207/5355
摘要： A method and computer system are provided for implementing a square root operation using an iterative converging approximation technique. The method includes fewer computations than conventional methods, and only includes computations which are simple to implement in hardware on a computer system, such as multiplication, addition, subtraction and shifting. Therefore, the methods described herein are adapted specifically for being performed on a computer system, e.g. in hardware, and allow the computer system to perform a square root operation with low latency and with low power consumption.
摘要翻译：提供了一种使用迭代收敛逼近技术实现平方根操作的方法和计算机系统。该方法包括比常规方法更少的计算，并且仅包括在计算机系统上的硬件中简单实现的计算，例如乘法，加法，减法和移位。因此，本文描述的方法专门用于在计算机系统上执行，例如，在硬件中，允许计算机系统以低延迟和低功耗执行平方根操作。

2. 发明授权

US09213639B2 Division of numerical values based on summations and memory mapping in computing systems 有权
标题翻译：基于计算系统中求和和内存映射的数值分割
公开(公告)号：US09213639B2
公开(公告)日：2015-12-15
申请号：US13626799
申请日：2012-09-25
申请人： Jeremy Branscome
发明人： Jeremy Branscome
IPC分类号： G06F12/06 , G06F7/535
CPC分类号： G06F12/0607 , G06F7/535 , G06F2207/5355 , G06F2207/5356
摘要： Divisions by numbers that are not divisible by two (2) can be performed in a computing system based on a summation that estimates and/or approximates the reciprocal of the dividing number or denominator value. By way of example, dividing by three (3) can be calculated based on a summation that approximates or estimates one third (⅓) represented as the sum of a selected group of the inverses of the powers of two (2) in a pattern, namely the sum of: ¼, 1/16, 1/64, 1/256, . . . ). Applications of the division techniques are virtually unlimited and include memory mapping of global memory addresses to memory channel addresses by dividing a global memory address into the number of memory channels, allowing memory mapping to be performed in an efficient manner even for large memory spaces using a number of memory channels that are not divisible by two, including prime numbers.
摘要翻译：不能被二（2）除尽的数字的划分可以在计算系统中基于估计和/或近似分割数或分母值的倒数的求和来执行。作为示例，可以基于近似或估计表示为模式中两（2）的幂的所选择的组的和的三分之一（1/3）的总和来计算除以三（3）即：¼，1/16，1/64，1/256，。。）。划分技术的应用实际上是无限制的，并且包括将全局存储器地址到存储器通道地址的存储器映射，通过将全局存储器地址划分为存储器通道的数量，允许以有效的方式执行存储器映射，即使对于使用不能被2整除的内存通道数，包括素数。

3. 发明授权

US08990278B1 Circuitry for computing mathematical functions 有权
标题翻译：用于计算数学函数的电路
公开(公告)号：US08990278B1
公开(公告)日：2015-03-24
申请号：US13275130
申请日：2011-10-17
申请人： Christopher M. Clegg
发明人： Christopher M. Clegg
IPC分类号： G06F1/02 , G06F7/38 , G06F7/552 , G06F7/544
CPC分类号： G06F7/544 , G06F7/535 , G06F7/5525 , G06F7/556 , G06F2207/5355 , G06F2207/5356
摘要： Methods and circuitry for evaluating reciprocal, square root, inverse square root, logarithm, and exponential functions of an input value, Y. In one embodiment, an approximate value, RA, of the reciprocal of Y is generated. One Newton-Raphson iteration is performed as a function of RA and Y, resulting in a truncated approximate value, R. R is multiplied by Y and 1 is subtracted, resulting in a reduced argument, A. A Taylor series evaluation of A is performed, resulting in an evaluated argument, B. B is multiplied by a post-processing factor for the final result.
摘要翻译：用于评估输入值Y的倒数，平方根，反平方根，对数和指数函数的方法和电路。在一个实施例中，生成Y的倒数的近似值RA。一个牛顿 - 拉夫逊迭代作为RA和Y的函数执行，产生一个截断的近似值，R被乘以Y，减去1，导致一个减少的参数A.执行A的泰勒级数评估，得到一个评估参数，B.B乘以最终结果的后处理因子。

4. 发明申请

US20120226730A1 System and Method for Testing Whether a Result is Correctly Rounded 有权
标题翻译：检查结果是否正确四舍五入的系统和方法
公开(公告)号：US20120226730A1
公开(公告)日：2012-09-06
申请号：US13038193
申请日：2011-03-01
申请人： Alexandru FIT-FLOREA
发明人： Alexandru FIT-FLOREA
IPC分类号： G06F7/552 , G06F7/38 , G06F7/44
CPC分类号： G06F7/483 , G06F7/4873 , G06F7/49942 , G06F7/5525 , G06F2207/5355 , G06F2207/5356
摘要： A computer-implemented method for executing a floating-point calculation where an exact value of an associated result cannot be expressed as a floating-point value is disclosed. The method involves: generating an estimate of the associated result and storing the estimate in memory; calculating an amount of error for the estimate; determining whether the amount of error is less than or equal to a threshold of error for the associated result; and if the amount of error is less than or equal to the threshold of error, then concluding that the estimate of the associated result is a correctly rounded result of the floating-point calculation; or if the amount of error is greater than the threshold of error, then testing whether the floating-point calculation constitutes an exception case.
摘要翻译：公开了一种用于执行浮点计算的计算机实现的方法，其中相关联的结果的精确值不能被表示为浮点值。该方法包括：产生关联结果的估计并将估计存储在存储器中; 计算估计的误差量; 确定误差量是否小于或等于相关结果的误差阈值; 并且如果误差量小于或等于误差阈值，则认为相关结果的估计是浮点计算的正确舍入结果; 或者如果错误量大于错误阈值，则测试浮点计算是否构成异常情况。

5. 发明申请

US20110289131A1 MACHINE DIVISION 有权
标题翻译：机械部
公开(公告)号：US20110289131A1
公开(公告)日：2011-11-24
申请号：US12785040
申请日：2010-05-21
申请人： Earl E. Swartzlander, JR. , Inwook Kong
发明人： Earl E. Swartzlander, JR. , Inwook Kong
IPC分类号： G06F7/44 , G06F7/552
CPC分类号： G06F7/535 , G06F2207/5355
摘要： Techniques are generally described that include methods, devices, systems and/or apparatus for dividing a numerator by a denominator. Some example methods may include selecting a first numerical factor stored in an electronic storage media. The first numerical factor may be multiplied by a numerator at least in part using a first logic circuit configured to perform multiplication. The first numerical factor may also be multiplied by a denominator. A second numerical factor may be calculated based, at least in part, on an approximation of a square of the difference between unity and the product of the first numerical factor and the denominator. The second numerical factor may be multiplied by the product of the numerator and the first numerical factor at least in part using the first logic circuit, to generate an approximation of a quotient of the numerator and the denominator.
摘要翻译：通常描述技术，其包括用分母除以分子的方法，装置，系统和/或装置。一些示例性方法可以包括选择存储在电子存储介质中的第一数值因子。至少部分地使用被配置为执行乘法的第一逻辑电路，第一数值因子可以乘以分子。第一数值因子也可以乘以分母。可以至少部分地基于第一数值因子和分母的单位和乘积之间的差的平方的近似来计算第二数值因子。至少部分地使用第一逻辑电路将第二数值因子乘以分子和第一数值因子的乘积，以产生分子和分母的商的近似。

6. 发明授权

US07921278B2 Early exit processing of iterative refinement algorithm using register dependency disable 失效
标题翻译：使用寄存器依赖关系禁用的迭代细化算法的早期退出处理
公开(公告)号：US07921278B2
公开(公告)日：2011-04-05
申请号：US12045313
申请日：2008-03-10
申请人： Adam James Muff , Matthew Ray Tubbs
发明人： Adam James Muff , Matthew Ray Tubbs
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30014 , G06F7/4873 , G06F7/535 , G06F9/30065 , G06F9/3838 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F2207/5355 , G06F2207/5356
摘要： An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in addition to disabling the register write enable of these instructions. By doing so, the latency of the algorithm is reduced and the performance is increased without the complexity and potential poor performance of compare and branch instructions that might otherwise be required.
摘要翻译：迭代细化算法的“提前退出”除了禁用寄存器写入之外，还通过有效禁用更新指令的写依赖性停止之后的读取以及禁止这些指令的寄存器写使能，对于算法的其余部分启用这些指令。通过这样做，降低了算法的等待时间，并且性能得到提高，而没有另外需要的比较和分支指令的复杂性和潜在的差的性能。

7. 发明授权

US07689642B1 Efficient accuracy check for Newton-Raphson divide and square-root operations 有权
标题翻译：牛顿 - 拉夫逊分割和平方根操作的有效精度检查
公开(公告)号：US07689642B1
公开(公告)日：2010-03-30
申请号：US11266838
申请日：2005-11-03
申请人： Leonard D. Rarick
发明人： Leonard D. Rarick
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F2207/5355
摘要： One embodiment of the present invention provides a system that efficiently performs an accuracy-check computation for Newton-Raphson divide and square-root operations. During operation, the system performs Newton-Raphson iterations followed by a multiply for the divide or square-root operation. This result is then rounded to produce a proposed result. Next, the system performs an accuracy-check computation to determine whether rounding the result to a desired precision produces the correct result. This accuracy-check computation involves performing a single pass through a multiply-add pipeline to perform a multiply-add operation. During this single pass, a Booth encoding of an operand in a multiply portion of the multiply-add pipeline is modified, if necessary, to cause an additional term for the accuracy-check computation to be added to the result of the multiply-add operation. In this way, the accuracy-check computation can be completed without requiring an additional pass through the multiply-add pipeline and without an additional partial-product row in the multiply-add pipeline.
摘要翻译：本发明的一个实施例提供了一种能够有效地执行牛顿 - 拉夫逊分割和平方根运算的精度检查计算的系统。在操作期间，系统执行牛顿 - 拉夫逊迭代，然后进行乘法除法或平方根操作。然后将该结果四舍五入以产生建议的结果。接下来，系统执行精度检查计算以确定将结果舍入到期望的精度是否产生正确的结果。此精确度检查计算涉及执行通过乘法加法管道的单次执行以执行乘法运算。在该单次通过期间，如果需要，修改乘法加法管道的乘法部分中的操作数的布斯编码，以便将精度检查计算的附加项添加到乘法运算的结果中。以这种方式，可以完成精度检查计算，而不需要额外的通过乘法加法管道，而在乘法加法管道中不需要额外的部分产品行。

8. 发明授权

US07676535B2 Enhanced floating-point unit for extended functions 有权
标题翻译：用于扩展功能的增强型浮点单元
公开(公告)号：US07676535B2
公开(公告)日：2010-03-09
申请号：US11236984
申请日：2005-09-28
申请人： David D. Donofrio , Xuye Li
发明人： David D. Donofrio , Xuye Li
IPC分类号： G06F7/38
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/535 , G06F2207/5355
摘要： An embodiment of the present invention is a technique to perform floating-point operations. A floating-point (FP) squarer squares a first argument to produce an intermediate argument. The first and intermediate arguments have first and intermediate mantissas and exponents. A FP multiply-add (MAD) unit performs a multiply-and-add operation on the intermediate argument, a second argument, and a third argument to produce a result having a result mantissa and a result exponent. The second and third arguments have second and third mantissas and exponents, respectively.
摘要翻译：本发明的实施例是执行浮点运算的技术。浮点（FP）正方形对齐第一个参数以产生中间参数。第一个和中间的论点有第一个和中间的尾随和指数。 FP乘法（MAD）单元对中间参数，第二参数和第三参数执行乘法和加法运算，以产生具有结果尾数和结果指数的结果。第二和第三个论点分别有第二和第三个尾声和指数。

9. 发明申请

US20060184594A1 Data processing apparatus and method for determining an initial estimate of a result value of a reciprocal operation 有权
标题翻译：用于确定倒数操作的结果值的初始估计的数据处理装置和方法
公开(公告)号：US20060184594A1
公开(公告)日：2006-08-17
申请号：US11058421
申请日：2005-02-16
申请人： David Lutz , Christopher Hinds , Dominic Symes , Simon Ford
发明人： David Lutz , Christopher Hinds , Dominic Symes , Simon Ford
IPC分类号： G06F15/00
CPC分类号： G06F7/535 , G06F9/30014 , G06F9/3004 , G06F2207/3824 , G06F2207/5354 , G06F2207/5355 , G06F2207/5356
摘要： The present invention provides a data processing apparatus and method for generating an initial estimate of a result value that would be produced by performing a reciprocal operation on an input value. The input value and the result value are either fixed point values or floating point values. The data processing apparatus comprises processing logic for executing instructions to perform data processing operations on data, and a lookup table referenced by the processing logic during generation of the initial estimate of the result value. The processing logic is responsive to an estimate instruction to reference the lookup table to generate, dependent on a modified input value that is within a predetermined range of values, a table output value. For a particular modified input value, the same table output value is generated irrespective of whether the input value is a fixed point value or a floating point value. The initial estimate of the result value is then derivable from the table output value. This provides a particularly efficient technique for performing the initial estimate generation within a data processing apparatus where the reciprocal operation may be performed on either fixed point values or floating point values.
摘要翻译：本发明提供了一种数据处理装置和方法，用于产生通过对输入值执行倒数操作而产生的结果值的初始估计。输入值和结果值是固定点值或浮点值。该数据处理装置包括执行用于对数据执行数据处理操作的指令的处理逻辑，以及在生成结果值的初始估计期间由处理逻辑引用的查找表。处理逻辑响应于估计指令以引用查找表，以根据在预定范围内的修改的输入值来生成表输出值。对于特定的修改输入值，无论输入值是固定点值还是浮点值，都会生成相同的表格输出值。结果值的初始估计值可从表输出值推导出来。这提供了用于在数据处理装置中执行初始估计生成的特别有效的技术，其中可以对固定点值或浮点值执行倒数操作。

10. 发明申请

US20060179092A1 System and method for executing fixed point divide operations using a floating point multiply-add pipeline 审中-公开
标题翻译：使用浮点乘法管线执行固定点除法运算的系统和方法
公开(公告)号：US20060179092A1
公开(公告)日：2006-08-10
申请号：US11055042
申请日：2005-02-10
申请人： Martin Schmookler
发明人： Martin Schmookler
IPC分类号： G06F7/00
CPC分类号： G06F7/535 , G06F7/483 , G06F2207/5355
摘要： A system and method for executing fixed point divide operations using a floating point multiply-add pipeline are provided. With the system and method, the floating point execution unit in a processor is modified to include elements that may be used to perform fixed point divide operations. These additional elements include a leading zero counter, a leading one counter, an estimate table unit, and a state machine. The fixed point divide operands are converted to a floating point format and an estimate of the reciprocal of the divisor is generated using estimate tables. These values are used in multiple passes through the floating point unit for calculating estimates of the quotient and corresponding error values. The estimates of the quotient are based on previous estimates of the quotient in a prior pass through the floating point unit and a corresponding error value. The final quotient estimate is truncated.
摘要翻译：提供了一种使用浮点乘法管线执行固定点除法运算的系统和方法。利用系统和方法，处理器中的浮点执行单元被修改为包括可用于执行定点除法运算的元件。这些附加元件包括前置零计数器，前导计数器，估计表单元和状态机。固定点除法操作数被转换为浮点格式，并使用估计表生成除数的倒数的估计。这些值用于多次通过浮点单元，用于计算商的估计值和相应的误差值。商的估计是基于先前通过浮点单位的商的先前估计和相应的误差值。最终商估计被截断。

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