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1. 发明申请

US20160170936A1 ARCHITECTURE FOR VECTOR MEMORY ARRAY TRANSPOSITION USING A BLOCK TRANSPOSITION ACCELERATOR 审中-公开
标题翻译：使用块式传输加速器的矢量存储器阵列传输架构
公开(公告)号：US20160170936A1
公开(公告)日：2016-06-16
申请号：US15049255
申请日：2016-02-22
申请人： ST-ERICSSON SA, EN LIQUIDATION
发明人： Yanmeng Sun , Liangliang Hu
IPC分类号： G06F15/80 , G06F7/78 , G06F9/30 , G06F17/16
CPC分类号： G06F15/8061 , G06F7/785 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30134 , G06F15/8076 , G06F17/16
摘要： A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.
摘要翻译：一种用于向量存储器阵列转置的系统和方法。该系统包括向量存储器，块转置加速器和地址控制器。向量存储器存储向量存储器阵列。块转置加速器读取向量存储器阵列内的数据块的向量。块转置加速器还将数据块向量的转置写入向量存储器。地址控制器确定向量访问顺序，并且块转置加速器根据向量存取顺序访问向量存储器阵列内的数据块的向量。

2. 发明授权

US09268746B2 Architecture for vector memory array transposition using a block transposition accelerator 有权
公开(公告)号：US09268746B2
公开(公告)日：2016-02-23
申请号：US12400572
申请日：2009-03-09
申请人： Yanmeng Sun , Liangliang Hu
发明人： Yanmeng Sun , Liangliang Hu
IPC分类号： G06F17/14 , G06F17/16 , G06F7/78
CPC分类号： G06F15/8061 , G06F7/785 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30134 , G06F15/8076 , G06F17/16
摘要： A system and method for vector memory array transposition. The system includes a vector memory, a block transposition accelerator, and an address controller. The vector memory stores a vector memory array. The block transposition accelerator reads a vector of a block of data within the vector memory array. The block transposition accelerator also writes a transposition of the vector of the block of data to the vector memory. The address controller determines a vector access order, and the block transposition accelerator accesses the vector of the block of data within the vector memory array according to the vector access order.

3. 发明申请

US20150058438A1 SYSTEM AND METHOD PROVIDING HIERARCHICAL CACHE FOR BIG DATA APPLICATIONS 审中-公开
标题翻译：为大数据应用提供分层缓存的系统和方法
公开(公告)号：US20150058438A1
公开(公告)日：2015-02-26
申请号：US14531171
申请日：2014-11-03
申请人： Fred Korangy , Hamed Ghasemzadeh , Mohsen Arjmandi , Reza Azmi
发明人： Fred Korangy , Hamed Ghasemzadeh , Mohsen Arjmandi , Reza Azmi
IPC分类号： H04L29/08
CPC分类号： H04L67/1097 , G06F7/5272 , G06F7/785 , H04L67/1095
摘要： The embodiments herein develop a system for providing hierarchical cache for big data processing. The system comprises a caching layer, a plurality of actors in communication with the caching layer, a machine hosting the plurality of actors, a plurality of replication channels in communication with the plurality of actors, a predefined ring structure. The caching layer is a chain of memory and storage capacity elements, configured to store a data from the input stream. The plurality of actors is configured to replicate the input data stream and forward the replicated data to the caching layer. The replication channels are configured to forward the replicated data from a particular actor to another actor. The predefined ring structure maps the input data to the replica actors.
摘要翻译：本文的实施例开发了一种用于为大数据处理提供分层缓存的系统。该系统包括缓存层，与缓存层通信的多个角色，承载多个角色的机器，与多个角色通信的多个复制频道，预定义的环形结构。缓存层是存储器和存储容量元件链，被配置为存储来自输入流的数据。多个演员被配置为复制输入数据流并将复制的数据转发到缓存层。复制通道配置为将复制数据从特定演员转发到另一个演员。预定义的环结构将输入数据映射到副本演员。

4. 发明申请

US20120151179A1 MEMORY STACKS MANAGEMENT 有权
标题翻译：存储堆栈管理
公开(公告)号：US20120151179A1
公开(公告)日：2012-06-14
申请号：US12963933
申请日：2010-12-09
申请人： Mark Gaertner , Mark Heath
发明人： Mark Gaertner , Mark Heath
IPC分类号： G06F12/10
CPC分类号： G06F12/0284 , G06F7/785 , G06F2212/657
摘要： A method for managing a memory stack provides mapping a part of the memory stack to a span of fast memory and a part of the memory stack to a span of slow memory, wherein the fast memory provides access speed substantially higher than the access speed provided by the slow memory.
摘要翻译：用于管理存储器堆栈的方法提供将存储器堆栈的一部分映射到快速存储器的一部分和存储器堆栈的一部分到慢存储器的跨度，其中快速存储器提供的访问速度显着高于由缓慢的记忆

5. 发明授权

US07610453B1 Reordering each array in a sequence of arrays 有权
标题翻译：以数组的顺序重新排列每个数组
公开(公告)号：US07610453B1
公开(公告)日：2009-10-27
申请号：US11527883
申请日：2006-09-27
申请人： Hemang Maheshkumar Parekh , Jeffrey Allan Graham , Hai-Jo Tarn , Elizabeth R. Cowie , Vanessa Yi-Mei Chou
发明人： Hemang Maheshkumar Parekh , Jeffrey Allan Graham , Hai-Jo Tarn , Elizabeth R. Cowie , Vanessa Yi-Mei Chou
IPC分类号： G06F12/00
CPC分类号： G06F7/785
摘要： Each array in a sequence of arrays is reordered. A first port receives in a first serial order a number of values in each array in the sequence and a second port transmits the values in a different second serial order. For each value in each array in the sequence, the address generator generates an address within a range of zero through one less than the number of values in the array. For each address from the generator, the memory performs an access to a location corresponding to the address in the memory. The access for each address includes a read from the location before a write to the location. For each array in the sequence, the writes for the addresses serially write the values of the array in the first serial order and the reads for the addresses serially read the values in the second serial order.
摘要翻译：一系列数组中的每个数组被重新排序。第一端口以第一串行顺序接收序列中每个阵列中的多个值，并且第二端口以不同的第二串行顺序发送值。对于序列中每个数组中的每个值，地址生成器将生成一个范围从零到小于数组中数值的地址。对于来自发生器的每个地址，存储器执行对与存储器中的地址相对应的位置的访问。每个地址的访问包括从写入位置之前的位置读取。对于序列中的每个数组，地址的写入以第一个串行顺序串行写入数组的值，并且地址的读取以串行顺序读取第二个串行顺序的值。

6. 发明授权

US07584343B2 Data reordering processor and method for use in an active memory device 有权
标题翻译：用于有源存储器件的数据重排序处理器和方法
公开(公告)号：US07584343B2
公开(公告)日：2009-09-01
申请号：US11582650
申请日：2006-10-17
申请人： Graham Kirsch
发明人： Graham Kirsch
IPC分类号： G06F12/00 , G06F15/80
CPC分类号： G06F7/785 , G06F9/3879 , G06F15/7821
摘要： An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. The active memory device includes a vector processing and re-ordering system coupled to the array control unit and the memory device. The vector processing and re-ordering system re-orders data received from the memory device into a vector of contiguous data, process the data in accordance with an instruction received from the array control unit to provide results data, and passes the results data to the memory device.
摘要翻译：主动存储装置包括从主机接收高级任务的命令引擎，并且向处理阵列控制单元产生对DRAM控制单元或ACU命令的DCU命令的相应组。 DCU命令包括也由命令引擎产生的存储器地址，并且ACU命令包括对应于存储处理阵列指令的阵列控制单元中的地址的指令存储器地址。有源存储器件包括耦合到阵列控制单元和存储器件的矢量处理和重新排序系统。向量处理和重新排序系统将从存储器装置接收到的数据重新排序为连续数据的向量，根据从阵列控制单元接收的指令处理数据以提供结果数据，并将结果数据传递给存储设备。

7. 发明授权

US07583687B2 Lock-free double-ended queue based on a dynamic ring 有权
标题翻译：基于动态环的无锁双端队列
公开(公告)号：US07583687B2
公开(公告)日：2009-09-01
申请号：US11325209
申请日：2006-01-03
申请人： Paul A. Martin , Guy L. Steele , Christine H. Flood
发明人： Paul A. Martin , Guy L. Steele , Christine H. Flood
IPC分类号： H04L12/28 , G06F9/46
CPC分类号： G06F9/52 , G06F7/785 , G06F9/544
摘要： One embodiment of the present invention provides a system that facilitates performing operations on a lock-free double-ended queue (deque). This deque is implemented as a doubly-linked list of nodes formed into a ring, so that node pointers in one direction form an inner ring, and node pointers in the other direction form an outer ring. The deque has an inner hat, which points to a node next to the last occupied node along the inner ring, and an outer hat, which points to a node next to the last occupied node along the outer ring. The system uses a double compare-and-swap (DCAS) operation while performing pop and push operations onto either end of the deque, as well as growing and shrinking operations to change the number of nodes that are in the ring used by the deque.
摘要翻译：本发明的一个实施例提供一种有助于在无锁双端队列（deque）上执行操作的系统。该deque被实现为形成环的节点的双向链表，使得在一个方向上的节点指针形成内环，并且在另一方向上的节点指针形成外环。德克有一个内帽，它指向沿着内圈的最后一个占用节点旁边的一个节点，以及一个外帽，它指向沿着外圈的最后占用节点旁边的一个节点。系统使用双重比较和交换（DCAS）操作，同时在deque的任一端执行弹出和推送操作，以及增长和缩小操作以更改由deque使用的环中的节点数。

8. 发明授权

US07487272B2 Using queue specific variable(s) to efficiently delete expired items in an ordered queue without necessarily checking each queued item's expiry time 失效
标题翻译：使用队列特定变量有效地删除有序队列中的过期项目，而不必检查每个排队的项目的到期时间
公开(公告)号：US07487272B2
公开(公告)日：2009-02-03
申请号：US11281987
申请日：2005-11-17
申请人： Andrew Ian Hickson , David John McCann
发明人： Andrew Ian Hickson , David John McCann
IPC分类号： G06F7/00 , G06F7/08
CPC分类号： G06F7/785 , G06F5/06
摘要： A method for deleting expired items in a queue data structure, the queue data structure comprising a sequential list of ordered data items including a queue head at one end of the sequential list and a queue tail at another end of the sequential list, wherein each data item includes an expiry time, the method comprising: generating a maximum interval value corresponding to a maximum time interval between an expiry time of a first item in the queue and an expiry time of a second item in the queue, wherein the second item is nearer the queue head than the first item; sequentially scanning the list of ordered items from the queue head; responsive to a determination that a scanned item is expired, deleting the scanned item; responsive to a determination that a scanned item will not expire for a time interval greater than the maximum interval value, terminating scanning of the list of ordered items.
摘要翻译：一种用于删除队列数据结构中的过期项目的方法，所述队列数据结构包括有序数据项的顺序列表，所述有序数据项包括所述顺序列表的一端的队列头和所述顺序列表的另一端的队列尾，其中每个数据项目包括到期时间，该方法包括：产生对应于队列中第一项目到期时间与队列中第二项目到期时间之间的最大时间间隔的最大间隔值，其中第二项目更接近队列头比第一项; 从队列头顺序扫描有序项目列表; 响应于确定扫描的项目已过期，删除所扫描的项目; 响应于确定扫描的项目将不会超过大于最大间隔值的时间间隔，终止对有序项目列表的扫描。

9. 发明申请

US20070038842A1 Data recording processor and method for use in an active memory device 有权
标题翻译：用于有源存储器件的数据记录处理器和方法
公开(公告)号：US20070038842A1
公开(公告)日：2007-02-15
申请号：US11582650
申请日：2006-10-17
申请人： Graham Kirsch
发明人： Graham Kirsch
IPC分类号： G06F15/00
CPC分类号： G06F7/785 , G06F9/3879 , G06F15/7821
摘要： An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. The active memory device includes a vector processing and re-ordering system coupled to the array control unit and the memory device. The vector processing and re-ordering system re-orders data received from the memory device into a vector of contiguous data, process the data in accordance with an instruction received from the array control unit to provide results data, and passes the results data to the memory device.
摘要翻译：主动存储装置包括从主机接收高级任务的命令引擎，并且向处理阵列控制单元产生对DRAM控制单元或ACU命令的DCU命令的相应组。 DCU命令包括也由命令引擎产生的存储器地址，并且ACU命令包括对应于存储处理阵列指令的阵列控制单元中的地址的指令存储器地址。有源存储器件包括耦合到阵列控制单元和存储器件的矢量处理和重新排序系统。向量处理和重新排序系统将从存储器装置接收到的数据重新排序为连续数据的向量，根据从阵列控制单元接收的指令处理数据以提供结果数据，并将结果数据传递给存储设备。

10. 发明申请

US20060143428A1 Semiconductor signal processing device 审中-公开
标题翻译：半导体信号处理装置
公开(公告)号：US20060143428A1
公开(公告)日：2006-06-29
申请号：US11282714
申请日：2005-11-21
申请人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Kazunori Saito
发明人： Hideyuki Noda , Kazutami Arimoto , Katsumi Dosaka , Kazunori Saito
IPC分类号： G06F15/00 , G06F7/48
CPC分类号： G06F7/785 , G11C5/025 , G11C7/1006 , G11C7/18 , G11C8/16 , G11C11/419 , G11C2207/104
摘要： An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.
摘要翻译：用于变换系统总线数据和处理数据的布置的正交存储器被放置在系统总线接口和存储处理数据的存储单元矩阵之间。正交存储器包括双端口存储器单元，并且将以位并行和字串行方式传送的数据串改变成字并行和位串行数据的数据串。可以增加执行并行操作处理的信号处理装置中的数据传送效率，而不会削弱处理的并行性。

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