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1. 发明申请

US20170278447A1 VECTOR DITHERING FOR DISPLAYS EMPLOYING SUBFIELDS HAVING UNEVENLY SPACED GRAY SCALE VALUES 有权
公开(公告)号：US20170278447A1
公开(公告)日：2017-09-28
申请号：US15077593
申请日：2016-03-22
申请人： SnapTrack, Inc.
发明人： Fahri Yaras , Chih-Hsiang Ho , Edward Buckley
IPC分类号： G09G3/20 , G09G5/10
CPC分类号： G09G3/2055 , G09G3/2029 , G09G3/2044 , G09G3/2051 , G09G3/3466 , G09G5/10 , G09G2310/0235 , G09G2320/0233 , G09G2320/0242
摘要： This disclosure provides systems, methods, apparatus, and computer readable media for generating images on a display using a dithering process that takes into account an uneven spacing of available gray scale values in at least one color subfield used to generate the images. The dithering process includes generating a set of initial color subfields, a set of quantized color subfields, and a set of final color subfields, which are then output on the display. The quantized color subfields an the final color subfields are derived based at least in part on the uneven spacing of gray scale values in at least one of the final color subfields.

2. 发明授权

US09591188B2 Cascaded bit sequences in display systems 有权
标题翻译：显示系统中的级联位序列
公开(公告)号：US09591188B2
公开(公告)日：2017-03-07
申请号：US14446374
申请日：2014-07-30
申请人： Brass Roots Technologies, LLC
发明人： Bradley William Walker
IPC分类号： G06F3/14 , H04N5/04 , H04N5/21 , G09G3/00 , G09G3/20 , G09G3/34
CPC分类号： H04N5/04 , G06F3/1423 , G09G3/002 , G09G3/2029 , G09G3/3426 , G09G2320/0646 , H04N5/21
摘要： The present disclosure pertains to a method for designing cascaded bit sequences for cascaded digital displays. The method avoids unwanted interactions between cascaded sequences in cascaded digital displays. By using sequences with a particular structure, cascaded sequences can be designed such that no sequence is affected by the others. The following rules must be followed in constructing the sequence. First, the display devices must be frame-locked, so that the timing relationship between the sequences is maintained throughout each frame. Second, for each display device, the ratio of bit plane weights must remain constant, regardless of the pixel data displayed on the other display device(s). Third, the amount of bit plane skew must remain constant, regardless of the pixel data displayed on the other display device(s). Fourth, bit plane phased leakage must be compensated for or avoided.
摘要翻译：本公开涉及用于级联数字显示器的级联比特序列的设计方法。该方法避免了级联数字显示器中级联序列之间的不必要的相互作用。通过使用具有特定结构的序列，可以设计级联序列，使得序列不受其他序列的影响。在构建序列时必须遵循以下规则。首先，显示设备必须被帧锁定，使得在每个帧中维持序列之间的时序关系。第二，对于每个显示设备，位平面权重的比率必须保持恒定，而与其他显示设备上显示的像素数据无关。第三，与其他显示设备上显示的像素数据无关，位平面偏移的量必须保持不变。第四，位平面分相泄漏必须补偿或避免。

3. 发明申请

US20160086574A1 ADAPTIVE FLICKER CONTROL 审中-公开
标题翻译：自适应扑克控制
公开(公告)号：US20160086574A1
公开(公告)日：2016-03-24
申请号：US14490775
申请日：2014-09-19
申请人： PIXTRONIX, INC.
发明人： Edward Buckley
IPC分类号： G09G5/10
CPC分类号： G09G5/10 , G09G3/2029 , G09G3/2033 , G09G3/3413 , G09G2310/0235 , G09G2320/0247 , G09G2320/0261 , G09G2320/064 , G09G2330/04 , G09G2340/0435 , G09G2360/144
摘要： This disclosure provides systems, methods and apparatus for reducing flicker in display devices. In some image formation processes, a controller can form an image by utilizing a set of color subfields and displaying subframes associated with each of the color subfields. In some implementations, the controller can determine a critical flicker frequency (CFF) associated with each subframe. The CFF for a subframe of a color is the minimum frequency at which the subframe of that color must be illuminated to avoid the perception of flicker by a viewer. If the CFF for any subframe is above an illumination frequency for that subframe, then the controller can employ flicker mitigation measures to reduce the perception of flicker of the subframe. In some implementations, the controller may carry out flicker mitigating measures such as dividing the display of subframes based on environmental factors such as ambient light.
摘要翻译：本公开提供了用于减少显示装置中的闪烁的系统，方法和装置。在一些图像形成处理中，控制器可以通过利用一组彩色子场并显示与每个彩色子场相关联的子帧来形成图像。在一些实现中，控制器可以确定与每个子帧相关联的临界闪烁频率（CFF）。用于子帧的CFF是该颜色的子帧必须被照亮的最小频率，以避免观察者感觉到闪烁。如果任何子帧的CFF高于该子帧的照明频率，则控制器可以采用闪烁缓解措施来减少子帧闪烁的感知。在一些实现中，控制器可以执行闪烁缓解措施，例如基于诸如环境光的环境因素来划分子帧的显示。

4. 发明授权

US09183773B2 Method and apparatus for representation of video and audio signals on a low-resolution display 有权
公开(公告)号：US09183773B2
公开(公告)日：2015-11-10
申请号：US13047489
申请日：2011-03-14
申请人： Artur B. Twarecki , Mark Batchelor
发明人： Artur B. Twarecki , Mark Batchelor
IPC分类号： G09G5/10 , G09G3/20 , G09G3/00
CPC分类号： G09G3/2029 , G09G3/001 , G09G2320/0247 , G09G2340/0407 , G09G2340/145
摘要： The method for the representation of video and audio signals on a low-resolution display panel, which includes the steps of: scaling the video or audio frame to fit the display panel, quantization of the video or audio signals to predetermined level values, temporal representation of video data by using the pulse density modulation, sending the signal pulses to the display panel. In further aspect the step of temporal representation contains the anti-flickering signal manipulation technique incorporating maximization of separation of the pulses during the pulse density modulation.

5. 发明申请

US20150036049A1 CASCADED BIT SEQUENCES IN DISPLAY SYSTEMS 有权
标题翻译：显示系统中的CASCADED BIT SEQUENCES
公开(公告)号：US20150036049A1
公开(公告)日：2015-02-05
申请号：US14446374
申请日：2014-07-30
申请人： Brass Roots Technologies, LLC
发明人： Bradley William Walker
IPC分类号： H04N5/04 , G06F3/14 , H04N5/21
CPC分类号： H04N5/04 , G06F3/1423 , G09G3/002 , G09G3/2029 , G09G3/3426 , G09G2320/0646 , H04N5/21
摘要： The present disclosure pertains to a method for designing cascaded bit sequences for cascaded digital displays. The method avoids unwanted interactions between cascaded sequences in cascaded digital displays. By using sequences with a particular structure, cascaded sequences can be designed such that no sequence is affected by the others. The following rules must be followed in constructing the sequence. First, the display devices must be frame-locked, so that the timing relationship between the sequences is maintained throughout each frame. Second, for each display device, the ratio of bit plane weights must remain constant, regardless of the pixel data displayed on the other display device(s). Third, the amount of bit plane skew must remain constant, regardless of the pixel data displayed on the other display device(s). Fourth, bit plane phased leakage must be compensated for or avoided.
摘要翻译：本公开涉及用于级联数字显示器的级联比特序列的设计方法。该方法避免了级联数字显示器中级联序列之间的不必要的相互作用。通过使用具有特定结构的序列，可以设计级联序列，使得序列不受其他序列的影响。在构建序列时必须遵循以下规则。首先，显示设备必须被帧锁定，使得在每个帧中维持序列之间的时序关系。第二，对于每个显示设备，位平面权重的比率必须保持恒定，而与其他显示设备上显示的像素数据无关。第三，与其他显示设备上显示的像素数据无关，位平面偏移的量必须保持不变。第四，位平面分相泄漏必须补偿或避免。

6. 发明授权

US08878754B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US08878754B2
公开(公告)日：2014-11-04
申请号：US13568154
申请日：2012-08-07
申请人： Keisuke Miyagawa , Hajime Kimura
发明人： Keisuke Miyagawa , Hajime Kimura
IPC分类号： G09G3/30 , G09G3/32 , G09G3/34
CPC分类号： G09G3/2092 , G09G3/2029 , G09G3/3233 , G09G2300/0465 , G09G2300/0842 , G09G2300/0861 , G09G2320/0233 , G09G2320/043 , G09G2320/0673 , G09G2330/02 , H01L27/1222 , H01L27/124 , H01L27/1255
摘要： The inventors found out that in the case of performing a low gray scale display in which a very small amount of current is supplied to a light emitting element, variations in threshold voltages of driving transistors become notable since the gate-source voltage is low. In view of this, the invention provides a display device in which variations in the threshold voltages of the driving transistors are reduced even in the low gray scale display, and a driving method thereof. According to the invention, a gate-source voltage of the driving transistor is set higher in the low gray scale display than that in the high gray scale display. As one mode to achieve this, different power source lines are provided for the low gray scale display and the high gray scale display and their potentials are set to be different.
摘要翻译：本发明人发现，在执行向发光元件供应非常少量的电流的低灰度显示的情况下，由于栅极 - 源极电压低，所以驱动晶体管的阈值电压的变化变得显着。鉴于此，本发明提供一种即使在低灰度级显示器中驱动晶体管的阈值电压的变化也减小的显示装置及其驱动方法。根据本发明，驱动晶体管的栅极 - 源极电压在低灰度显示器中比在高灰度级显示器中高。作为实现这一点的一种模式，为低灰度显示和高灰度显示提供不同的电源线，并且它们的电位被设置为不同。

7. 发明授权

US08674910B2 Display panel driving method, display apparatus, display panel driving apparatus and electronic apparatus 有权
标题翻译：显示面板驱动方法，显示装置，显示面板驱动装置和电子设备
公开(公告)号：US08674910B2
公开(公告)日：2014-03-18
申请号：US12153478
申请日：2008-05-20
申请人： Mitsuru Asano
发明人： Mitsuru Asano
IPC分类号： G09G3/30
CPC分类号： G09G5/10 , G09G3/2029 , G09G3/3225 , G09G2320/0247 , G09G2320/0261 , G09G2320/064
摘要： In the present invention, there is provided a display panel driving method of the type wherein the total light emitting period length within a one-field period is controlled to variably control the peak luminance level of a display panel, including the step of: variably controlling, where the one-field period has N light emitting periods, N being equal to or greater than 2, the end timing of the ith light emitting period and the start timing of the i+1th light emitting period so as to satisfy the total light emitting period length within the one-field period, i being an odd number which satisfies 1≦i≦N−1 while i+1 satisfies 2≦i+1≦N.
摘要翻译：在本发明中，提供了一种显示面板驱动方法，其中控制一场场周期内的总发光周期长度以可变地控制显示面板的峰值亮度水平，包括以下步骤：可变地控制其中单场周期具有N个发光周期，N等于或大于2，第i个发光周期的结束定时和第i + 1个发光周期的开始定时，以满足总光线在1场周期内发射周期长度，i是满足1 @ i @ N-1的奇数，而i + 1满足2 @ i + 1 @ N。

8. 发明授权

US08599228B2 Image processing apparatus, display apparatus, and image displaying system 有权
标题翻译：图像处理装置，显示装置和图像显示系统
公开(公告)号：US08599228B2
公开(公告)日：2013-12-03
申请号：US12373943
申请日：2007-07-17
申请人： Daigo Miyasaka , Masao Imai , Fujio Okumura
发明人： Daigo Miyasaka , Masao Imai , Fujio Okumura
IPC分类号： G09G5/10
CPC分类号： G09G3/2029 , G09G3/001 , H04N13/341 , H04N13/398 , H04N2013/403
摘要： An image processing apparatus, a display apparatus and an image displaying system wherein both secure and public images can be efficiently displayed with high quality without lowering the contrast of the public images. There are included a memory (101) that stores the image data of input secure and reversed images; a data assigning circuit (102) that assigns a pulse train, which has the same pulse width for the secure images and reversed images stored in the memory (101), as an image signal consisting of a pulse train to be used for displaying images on a display apparatus of PWM drive mode in which one frame is divided into a plurality of subfields to express brightness gray scales; and a shutter spectacle control signal generating circuit (103) that outputs a shutter control signal only during outputting of image signals in accordance with the secure images. The secure and reversed images have such a relationship that they become image data of images having no correlation with the secure images when the brightness values of their respective image data are added together for each pixel.
摘要翻译：图像处理装置，显示装置和图像显示系统，其中可以高质量地高效地显示安全和公共图像，而不会降低公共图像的对比度。包括存储输入安全和反转图像的图像数据的存储器（101）; 数据分配电路（102），其分配具有与存储在存储器（101）中的安全图像和反转图像相同的脉冲宽度的脉冲序列作为由用于显示图像的脉冲串组成的图像信号一种PWM驱动模式的显示装置，其中一帧被分成多个子场以表示亮度灰度级; 以及仅在根据安全图像输出图像信号期间输出快门控制信号的快门眼镜控制信号发生电路（103）。安全和反转的图像具有这样的关系，即当它们各自的图像数据的亮度值被加到一起用于每个像素时，它们变成与安全图像无关的图像的图像数据。

9. 发明申请

US20130100177A1 SPATIALLY MULTIPLEXED PULSE WIDTH MODULATION 有权
标题翻译：空间多路复用脉冲宽度调制
公开(公告)号：US20130100177A1
公开(公告)日：2013-04-25
申请号：US13660547
申请日：2012-10-25
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Todd A. Clatanoff , Philip S. King , Jeffrey M. Kempf
IPC分类号： G09G5/10
CPC分类号： G09G5/10 , G09G3/2018 , G09G3/2029 , G09G2320/0247 , G09G2320/0266 , G09G2320/0285 , G09G2320/064
摘要： A process of operating a PWM display system wherein some display data bits are assigned substantially equal time weights. Display data codewords are defined for every pixel intensity value to form display data codeword tables so that there are at least as many display data codeword tables as the number of display data bits with substantially equal time weights. The display pixel is subsequently operated in a digital manner according to the display data codeword in the selected display data codeword table to display a desired pixel intensity value. The display data codeword tables are configured so that immediately adjacent display pixels are operated so that identical pixel intensity values are displayed with different temporal sequences.
摘要翻译：一种操作PWM显示系统的过程，其中一些显示数据位被指定为基本相等的时间权重。为每个像素强度值定义显示数据码字以形成显示数据码字表，使得至少与显示数据位数相同的显示数据码字表与基本相等的时间权重。显示像素随后根据所选择的显示数据码字表中的显示数据码字以数字方式操作，以显示期望的像素强度值。显示数据码字表被配置为使得紧邻的显示像素被操作，使得以不同的时间序列显示相同的像素强度值。

10. 发明授权

US08305300B2 Method for driving plasma display panel and plasma display device 失效
标题翻译：驱动等离子体显示面板和等离子体显示装置的方法
公开(公告)号：US08305300B2
公开(公告)日：2012-11-06
申请号：US11816030
申请日：2007-02-26
申请人： Kunihiro Mima , Kosuke Makino , Tooru Kawase
发明人： Kunihiro Mima , Kosuke Makino , Tooru Kawase
IPC分类号： G09G3/28
CPC分类号： G09G3/2029 , G09G3/2922 , G09G3/2927 , G09G3/294 , G09G3/2942 , G09G3/296 , G09G3/298 , G09G2310/0267 , G09G2320/0238
摘要： The method for driving a plasma display panel effects control of the sub-fields in a manner that at least one sub-filed carries out, in its initializing period, an all-cell initializing operation on the discharge cells and the plurality of sub-fields other than the aforementioned sub-field selectively carry out an addressing operation in each discharge cell; at the same time, two or more predetermined sub-fields carry out an addressing operation only when at least one sub-field had an addressing operation after the all-cells initializing operation; and an unusual-charge erase period, where scan electrodes SC-SCn undergo application of voltage with a rectangular waveform, is provided after the initializing period of at least one sub-field of the predetermined sub-fields.
摘要翻译：用于驱动等离子体显示面板的方法以至少一个子场在其初始化时段内对放电单元和多个子场进行全单元初始化操作的方式实现子场的控制除了上述子场之外，选择性地执行每个放电单元中的寻址操作; 同时，仅当至少一个子场在全单元初始化操作之后具有寻址操作时，两个或更多个预定子场才执行寻址操作; 并且在预定子场的至少一个子场的初始化周期之后提供扫描电极SC-SCn经受矩形波形施加电压的异常电荷擦除周期。

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